Semiconductor Package Wafer-Level Back-Side Connections
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Solution Overview
Problem
Conventional semiconductor packaging methods for vertical power MOSFET devices require additional assembly steps after wafer singulation, increasing costs and fabrication time, and struggle with achieving a small footprint and low electrical resistance while facilitating efficient thermal dissipation and mechanical support.
Innovation Solution
A semiconductor device package design that includes a support substrate attached to the device substrate, allowing for wafer-level processing, with back conductive layers and extensions enabling electrical connections to a common plane without increasing package size, and using a support substrate for mechanical and thermal support.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If conventional packaging methods with wire bonding are used, then electrical connections can be established, but the package size increases and the number of device packages per wafer decreases
Solution Approach 1:
The patent extends electrical connections from the back surface of the semiconductor device to the front surface by creating conductive paths through the substrate thickness, allowing all connections to be coplanar and eliminating the need for additional packaging space for connection extension
2Ease of operation
If back surface connections are extended to the front surface, then electrical connections are facilitated, but the device package size increases
Solution Approach 1:
The invention utilizes the third dimension (substrate thickness) to create conductive paths that extend connections from the back to front surface, then brings them coplanar through planarization, achieving connection extension without increasing the device footprint
Solution Approach 2:
The patent changes the physical state and position of conductive materials through deposition, electroplating, and planarization processes, transforming the connection structure to achieve coplanar connections with minimized footprint
3Productivity
If wafer level processing is implemented, then manufacturing efficiency increases, but achieving small footprint and low resistance becomes more difficult
Solution Approach 1:
The patent performs connection extension and planarization at the wafer level before dicing, preliminarily establishing all electrical connections and minimizing footprint for all devices simultaneously, which enables subsequent precise control of resistance and footprint in individual device packages
4Object-generated harmful factors
If traditional wire bonding is used, then electrical connections can be established, but thermal dissipation and mechanical support are insufficient
Solution Approach 1:
The patent merges the functions of electrical connection, thermal dissipation, and mechanical support into a single integrated substrate structure, eliminating the need for separate wire bonding and additional support elements, thereby improving thermal dissipation without increasing device complexity
Data Source
AI summary
A semiconductor device package die and method of manufacture are disclosed. The device package die may comprise a device substrate having one or more front electrodes located on a front surface of the device substrate and electrically connected to one or more corresponding device regions formed within the device substrate proximate the front surface. A back conductive layer is formed on a back surface of the device substrate. The back conductive layer is electrically connected to a device region formed within the device substrate proximate a back surface of the device substrate. One or more conductive extensions are formed on one or more corresponding sidewalls of the device substrate in electrical contact with the back conductive layer, and extend to a portion of the front surface of the device substrate. A support substrate is bonded to the back surface of the device substrate.