Semiconductor Backside Wiring With Air Gaps for Lower Rail Resistance
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Solution Overview
Problem
Conventional semiconductor fabrication methods face challenges in forming power rails and vias on the backside of ICs with reduced resistance and coupling capacitance, leading to increased voltage drop and power consumption as circuits scale down.
Innovation Solution
Incorporation of backside metal wiring layers with wider dimensions and backside air gaps to reduce power rail resistance and coupling capacitance, along with a bottom self-aligned capping layer for isolation between gate stacks and power rails, using dielectric materials with high dielectric constants to enhance IC performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If power rails are scaled down with circuit dimensions, then device density increases, but voltage drop and power consumption increase
Solution Approach 1:
The patent introduces backside power rails that extend from the front surface through the substrate to the back surface, utilizing the third dimension (vertical depth) to create additional power distribution pathways. This dimensional transition allows power rails to bypass the planar scaling limitations, providing low-resistance paths that reduce voltage drop while maintaining high device density on the front surface.
Solution Approach 2:
The backside power rails are nested within the substrate structure, with first and second power rails positioned at different depths or locations within the substrate thickness. This nesting approach allows multiple power distribution layers to coexist without occupying additional planar area, thereby reducing resistance while preserving device density.
2Ease of manufacture
If conventional fabrication methods are used for backside power rails, then manufacturing simplicity is maintained, but coupling capacitance and resistance remain high
Solution Approach 1:
The patent introduces a dielectric layer as an intermediary between the backside power rails and the transistor structures. This dielectric intermediary reduces coupling capacitance between the power rails and active devices, improving reliability while the standard semiconductor fabrication processes maintain ease of manufacture.
3Reliability
If air gaps are introduced between gate stacks and power rails, then coupling capacitance is reduced, but fabrication complexity increases
Solution Approach 1:
The fabrication process uses self-aligned techniques where the air gaps are automatically positioned relative to the gate stacks and power rails through conformal deposition and etch-stop mechanisms. This self-alignment eliminates the need for additional lithography and alignment steps, reducing fabrication complexity while achieving the desired coupling capacitance reduction.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution reduces power rail resistance and coupling capacitance, enabling faster IC operation and improved TDDB performance by eliminating leakage paths and reducing voltage drop.
Implementation Method 1
backside air gaps to reduce power rail resistance and coupling capacitance
Implementation Method 2
using dielectric materials with high dielectric constants to enhance IC performance
Data Source
AI summary
A semiconductor structure includes first and second epitaxial features, at least one semiconductor channel layer connecting the first and second epitaxial features, and a gate structure engaging the semiconductor channel layer. The first and second epitaxial features, the semiconductor channel layer, and the gate structure are at a frontside of the semiconductor structure. The semiconductor structure also includes a backside metal wiring layer at a backside of the semiconductor structure, and a backside conductive contact electrically connecting the first epitaxial feature to the backside metal wiring layer. The backside metal wiring layer is spaced away from the gate structure with an air gap therebetween.