Semiconductor Device Bandwidth Option Switching Charge Sharing

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Solution Overview

Problem

Conventional semiconductor devices experience X4 flipping errors due to charge sharing between bit lines and local lines during data bandwidth option switching, leading to data corruption and potential read operation failures.

Innovation Solution

A semiconductor device design that includes a common coupling block, first and second coupling blocks, and a control block to manage data bandwidth options by selectively enabling write paths and disconnecting unused paths during write operations, preventing charge sharing between bit lines and local lines.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If data bandwidth option is set to X4 mode and write operations are performed through four input/output pads, then data is transmitted through fewer pads reducing bandwidth, but charge sharing occurs between bit lines and local lines causing X4 flipping errors

Engineering Contradiction:
Improvedata bandwidthVSAvoiddata integrity
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The semiconductor device divides the data transmission paths into separate segments: bit lines for reading data from memory cells and local lines for writing data to memory cells. The coupling blocks selectively connect these segments based on operation type, preventing charge sharing between them during X4 mode write operations while maintaining full connectivity during read operations.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The coupling blocks dynamically adjust the connectivity between bit lines and local lines based on the current operation mode (read or write) and data bandwidth option (X8 or X4). This dynamic reconfiguration ensures that during X4 write operations, the coupling blocks prevent charge sharing while maintaining proper data transmission paths, thus resolving the contradiction between reduced bandwidth and data integrity.

Inventive Principle:
Principle #15Dynamics

2Reliability

If coupling blocks are used to manage data paths during write operations, then charge sharing is prevented improving data integrity, but device complexity increases due to additional control logic

Engineering Contradiction:
Improvedata integrityVSAvoidcontrol logic complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The coupling blocks serve multiple functions: they manage both read and write operations, support both X8 and X4 data bandwidth modes, and prevent charge sharing during X4 write operations. By designing a universal control mechanism that handles multiple operation types and bandwidth options, the patent reduces the need for separate dedicated control circuits for each scenario, thereby managing device complexity while maintaining data integrity.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Solution Approach 2:

The coupling blocks are configured in advance to recognize and respond to different operation modes and bandwidth options. The control logic prepares the appropriate coupling configuration before data transmission begins, ensuring that charge sharing is prevented from the outset during X4 write operations without requiring complex real-time adjustments during the actual data transfer.

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS9418725B2Semiconductor device and method of driving the same
Publication Date: 2016.08.16 SK HYNIX INC
  • US9418725B2 patent drawing
  • US9418725B2 patent drawing
  • US9418725B2 patent drawing

AI summary

A semiconductor device may include a common coupling block suitable for coupling a plurality of first data lines to a plurality of second data lines in response to a common control signal, which is activated regardless of a data bandwidth option mode, a first coupling block suitable for coupling a part of the plurality of second data lines to a part of a plurality of third data lines in response to a first operation control signal, a second coupling block suitable for coupling the other part of the plurality of second data lines to the other part of the plurality of third data lines in response to a second operation control signal, and a control block suitable for activating one or more of the first and second operation control signals based on the data bandwidth option mode, during a data input/output operation.