Semiconductor Bank Group Address Generation Circuit
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Solution Overview
Problem
Current semiconductor devices face challenges in efficiently performing column operations across multiple bank groups due to limitations in bank address generation and control pulse management, leading to increased operation time and power consumption.
Innovation Solution
The semiconductor device incorporates a bank group selection signal generation circuit and a bank group address generation circuit, which store and output bank addresses based on command pulses, allowing for separate and efficient column operations across multiple bank groups by generating appropriate control pulses and addresses.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If bank addresses are stored and output at different moments using separate control pulses, then column operation efficiency is improved and power consumption is reduced, but device complexity increases due to additional control circuits
Solution Approach 1:
The patent divides the control of bank address operations into separate phases: input control pulses for storing bank addresses and output control pulses for outputting them as bank group selection signals. This segmentation allows independent optimization of each phase, improving column operation efficiency while managing complexity through modular control
Solution Approach 2:
The patent stores bank addresses in advance during the input phase before they are needed for bank group selection. By performing the address storage operation preliminarily and separately from the output operation, the system prepares data ahead of time, enabling more efficient column operations across multiple bank groups
2Loss of time
If separate control pulses are used for input and output operations, then operation time is reduced, but manufacturing complexity increases
Solution Approach 1:
The patent employs periodic control pulses with distinct timing phases - input control pulses for address storage and output control pulses for address output. This periodic, phased approach separates operations in time, reducing overall operation time while using standardized pulse generation techniques that are manufacturable
3Measurement precision
If bank addresses are stored based on command pulses, then address accuracy is improved, but power consumption increases
Solution Approach 1:
The patent stores bank addresses preliminarily in response to command pulses before they are needed for bank group selection. This preliminary storage captures the address accurately when the command is issued, then holds it ready for output, ensuring address accuracy while avoiding repeated high-power operations
Solution Approach 2:
The bank group selection signal generation circuit automatically outputs the stored bank address as a bank group selection signal when the appropriate output control pulse is received, without requiring additional external intervention. This self-service mechanism ensures accurate address output while minimizing additional power consumption
Data Source
AI summary
A semiconductor device includes a bank group selection signal generation circuit and a bank group address generation circuit. The bank group selection signal generation circuit stores a bank address based on a command pulse generated to perform a read operation or a write operation. The bank group selection signal generation circuit outputs the stored bank address as a bank group selection signal. The bank group address generation circuit generates a bank group address and an internal bank group address for performing a column operation of a cell array included in a bank group selected based on the bank group selection signal.