Semiconductor Memory Bank Conflict Resolution
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Solution Overview
Problem
Existing semiconductor devices face delays due to memory bank conflicts when multiple processing systems access the same memory bank simultaneously, as they do not effectively determine or prevent such conflicts.
Innovation Solution
A semiconductor device configuration that includes a memory controller, image processing sections, and a CPU, which determines and manages access start bank numbers to prevent bank conflicts by using different bank numbers for concurrent access, ensuring that the first and second image processing sections access distinct bank numbers to avoid conflicts.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multiple processing systems access the same memory bank simultaneously, then processing parallelism is improved, but memory bank conflicts occur causing processing delays
Solution Approach 1:
The memory is divided into multiple independent banks, allowing different processing systems to access different banks simultaneously. The memory address space is segmented such that consecutive addresses are distributed across different banks, enabling parallel access without conflict.
Solution Approach 2:
The patent introduces a bank dimension to the memory address space, transforming the traditional single-dimension address mapping into a multi-dimensional structure. This allows simultaneous access to different banks from multiple processing systems by utilizing the bank dimension for address distribution.
2Loss of time
If bank conflict avoidance mechanisms are implemented, then processing delays are reduced, but device complexity increases
Solution Approach 1:
The memory address translation mechanism automatically distributes addresses to different banks without requiring external conflict detection or arbitration. The address translation unit inherently performs bank conflict avoidance through its address mapping algorithm, eliminating the need for separate conflict detection circuits.
Solution Approach 2:
The patent changes the address mapping parameters by introducing bank number calculations based on address bits. By modifying how addresses are translated and distributed across banks, the system achieves conflict-free parallel access through parameter-based address distribution rather than complex control logic.
Data Source
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AI summary
To provide a semiconductor device which suppresses a delay in processing. The semiconductor device is equipped with a plurality of read units which read data stored across a plurality of banks in a memory having the banks, and an access method managing section which, when one of the read units reads the data, determines a read start bank number being a bank number to start reading according to operation situations of the read units excepting the one read unit, and instructs the determined read start bank number to the one read unit.