Semiconductor Bank Control Circuit for Simultaneous Data Output
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Solution Overview
Problem
Semiconductor devices face challenges in efficiently performing column operations across multiple bank groups, particularly in simultaneous data output and input operations, which affects performance and energy consumption.
Innovation Solution
The semiconductor device incorporates a column operation control circuit and a bank column address generation circuit to generate control signals and pulses for synchronizing data operations across multiple banks, enabling simultaneous data output in read mode and sequential data input in write mode, utilizing synthesis control pulses and internal control pulses to manage bank selection and data transfer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If data are inputted into a second bank after data are inputted into a first bank (sequential write mode), then the device complexity is reduced, but the productivity is decreased due to sequential rather than simultaneous operations
Solution Approach 1:
The patent implements dynamic operation modes that can switch between sequential and simultaneous bank operations. The column operation control circuit dynamically adjusts its behavior based on the operation mode signal, enabling simultaneous data input to multiple banks in write mode while maintaining sequential operation in other modes, thus resolving the contradiction between device complexity and productivity
2Productivity
If data in a first bank and data in a second bank are simultaneously outputted (simultaneous read mode), then the productivity is improved, but the device complexity increases due to additional control signals and circuits
Solution Approach 1:
The patent segments the control functions into distinct modules: a column operation control circuit that generates control signals, a bank column address generation circuit that generates addresses, and a synthesis control pulse generation circuit that provides timing synchronization. This segmentation enables simultaneous bank operations while managing complexity through modular design
Solution Approach 2:
The patent introduces intermediary control circuits that mediate between the external interface and the internal bank structures. The column operation control circuit and bank column address generation circuit act as intermediaries that coordinate simultaneous operations across multiple banks, reducing the complexity burden on the core memory array
3Adaptability or versatility
If column operations are performed across multiple bank groups, then the adaptability is improved, but the use of energy increases due to simultaneous operations across multiple banks
Solution Approach 1:
The patent employs periodic synthesis control pulses that are generated in synchronization with read and write command pulses. These periodic pulses enable selective activation of bank operations, allowing the system to adapt to different access patterns while controlling energy consumption by activating only the necessary banks during each periodic cycle
Data Source
AI summary
A semiconductor device includes a column operation control circuit and a bank column address generation circuit. The column operation control circuit generates first and second bank address control signals as well as first and second bank control pulses from first and second bank selection signals in response to a synthesis control pulse such that data in a first bank and data in a second bank are simultaneously outputted in a first mode. The bank column address generation circuit generates first and second bank column addresses for selecting the first and second banks from a column address in response to the first and second bank address control signals.