Semiconductor Barrier Pattern with Inclined Surfaces
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Solution Overview
Problem
The challenge lies in manufacturing three-dimensional nonvolatile memory devices with improved loading characteristics and integration, as existing two-dimensional devices have reached integration limits due to limitations in stack structure thickness and resistance values.
Innovation Solution
A semiconductor device manufacturing method involving alternately forming sacrificial and insulating layers, forming channel patterns, and creating conductive layers with barrier patterns having inclined inner surfaces and metal patterns, which allows for increased metal pattern volume without increasing conductive layer thickness, thereby enhancing loading characteristics.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the thickness of conductive layers is increased to improve loading characteristics, then the resistance values decrease, but the device height and integration density are compromised
Solution Approach 1:
The invention transitions from increasing thickness (one dimension) to increasing lateral area (two dimensions) by forming metal patterns that extend between adjacent channel patterns. This allows resistance reduction through increased conductive cross-section area without increasing the vertical thickness of the conductive layer, thereby maintaining integration density while improving loading characteristics.
2Reliability
If the metal pattern volume is increased to reduce resistance values, then the loading characteristics improve, but the conductive layer thickness must be increased
Solution Approach 1:
The metal patterns are designed to extend laterally between adjacent channel patterns in the horizontal plane, increasing the effective conductive cross-section area without increasing vertical thickness. This dimensional shift allows resistance reduction while maintaining the same conductive layer thickness, solving the contradiction between resistance improvement and thickness increase.
Solution Approach 2:
The metal patterns are nested within the conductive layer structure, positioned between channel patterns and integrated into the existing vertical stack. This nesting allows additional conductive material to be incorporated without adding external dimensions, effectively reducing resistance while maintaining compact integration.
3Quantity of substance
If two-dimensional memory device integration is increased, then the storage capacity improves, but the integration limit is reached due to stack structure thickness constraints
Solution Approach 1:
The invention moves from vertical stacking (one-dimensional growth) to lateral expansion (two-dimensional growth) by forming metal patterns that extend between channel patterns. This allows continued integration improvement without increasing stack thickness, effectively overcoming the physical limits of vertical scaling.
Data Source
AI summary
The invention is related to a method for manufacturing a semiconductor device having a barrier pattern. The method includes alternately forming first sacrificial layers and insulating layers forming channel patterns penetrating the first sacrificial layers and the insulating layers, and forming a slit penetrating the first sacrificial layers and the insulating layers. In order to form the barrier pattern, the method also includes forming openings by removing the first sacrificial layers through the slit, and respectively forming conductive layers in the openings. The conductive layers include first barrier patterns having inclined inner surfaces and metal patterns in the first barrier patterns.