Semiconductor Contact Hole Critical Dimension Control via Barrier Layer
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Solution Overview
Problem
In semiconductor manufacturing, the increasing density of devices on a wafer leads to challenges in forming contact holes due to exposure resolution limitations, causing the second lithographic process's photo resist to be poisoned or contaminated, which affects the critical dimension control.
Innovation Solution
The method involves forming barrier layers to cover the patterned hard mask and aperture surfaces, preventing the patterned resist from contamination and ensuring precise critical dimension control by using nitrogen-free materials like silicon oxide layers formed through atomic layer deposition.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If double-exposure patterning technology is used to form contact holes, then the exposure resolution limitation is overcome and contact holes can be formed at higher device density, but the photo resist of the second lithographic process becomes poisoned and contaminated by compositions from the first lithographic process, affecting critical dimension control
Solution Approach 1:
A barrier layer is introduced as an intermediary between the hard mask layer and the photo resist layer. This barrier layer prevents direct contact and chemical interaction between the photo resist and compositions from previously exposed areas, eliminating the poisoning effect while allowing the double-exposure patterning process to proceed with precise critical dimension control
Solution Approach 2:
The patent segments the original single mask layer into two distinct layers: a hard mask layer for structural definition and a barrier layer for chemical protection. This segmentation allows each layer to perform its specific function independently, with the hard mask providing pattern definition and the barrier layer preventing contamination of the photo resist
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively prevents resist poisoning and contamination, improving the control of critical dimensions in semiconductor structures by maintaining resist integrity during etching processes.
Implementation Method 1
nitrogen-free materials like silicon oxide layers formed through atomic layer deposition
Data Source
AI summary
A method of fabricating a semiconductor structure for improving critical dimension control is provided in the present invention. The method includes the following steps. An inter metal dielectric (IMD) layer is formed on a semiconductor substrate, a patterned hard mask layer is formed on the IMD layer, and a first aperture is formed in the IMD layer. A first barrier layer is formed on the patterned hard mask layer and a surface of the first aperture, a first patterned resist is formed on the first barrier layer, and an etching process is performed to form a second aperture in the IMD layer by using the first patterned resist as a mask. The first patterned resist is kept from being poisoned because of the first barrier layer, and the critical dimension control of the semiconductor structure may be improved accordingly.