Semiconductor Device Barrier Layer for DRAM Node Resistance
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Solution Overview
Problem
The integration of dynamic random access memory (DRAM) semiconductor devices leads to reduced memory cell area and increased node resistance due to oxidation during dielectric layer formation, causing bridge phenomena between electrodes and reliability issues.
Innovation Solution
A semiconductor device design featuring a lower electrode structure with a cylindrical first electrode pattern, a barrier layer, and a second electrode pattern in a space defined by the barrier layer, which suppresses excessive oxidation and maintains low resistance by blocking reaction gases, thereby preventing bridge formation and maintaining reliable node resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If integration of DRAM is increased to reduce memory cell area, then device density improves, but node resistance increases due to oxidation during dielectric layer formation
Solution Approach 1:
A barrier layer is introduced as an intermediary between the lower electrode and the dielectric layer. This barrier layer prevents reaction gases from reaching and oxidizing the lower electrode during dielectric layer formation, thereby maintaining low node resistance while allowing high device density integration
Solution Approach 2:
The patent employs a dual lower electrode structure with a first lower electrode pattern and a second lower electrode pattern positioned in spaces defined by the barrier layer. This copied/repeated electrode structure increases the effective electrode area and reduces resistance while maintaining compact memory cell dimensions for high density
2Reliability
If dielectric layer formation is performed on lower electrode structures, then capacitor insulation is improved, but excessive oxidation occurs causing resistance increase and bridge phenomena
Solution Approach 1:
The barrier layer serves as a protective intermediary that blocks reaction gases during dielectric layer formation, preventing oxidation of the lower electrode while allowing the dielectric layer to be properly formed for capacitor insulation
Solution Approach 2:
The barrier layer is formed on the lower electrode structure before the dielectric layer formation process begins. This preliminary protective action prevents oxidation from occurring during subsequent dielectric layer deposition, eliminating the need for corrective measures after oxidation has damaged the electrode
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively reduces the rate of resistance increase and bridge fail bits in semiconductor devices, enhancing the reliability and performance of memory chips by preventing oxidation-induced resistance increases and bridge phenomena.
Implementation Method 1
oxidation during dielectric layer formation, causing bridge phenomena between electrodes and reliability issues
Data Source
AI summary
A semiconductor device includes a lower electrode structure, an upper electrode structure, and a dielectric layer between the lower and upper electrode structures and on side surfaces and an upper surface of the lower electrode structure. The lower electrode structure includes a first lower electrode pattern having a cylindrical shape, a barrier layer on the first lower electrode pattern, and a second lower electrode pattern in a space defined by the barrier layer.