Semiconductor Barrier Layer Prevents Paste Penetration

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Solution Overview

Problem

In semiconductor devices, conductive paste can penetrate into the adhesive resin layer during chip mounting, leading to reduced insulation between electrode terminals, which affects the electrical connectivity and reliability of the device.

Innovation Solution

A semiconductor device design that includes an interconnect substrate with an adhesive resin layer and a barrier layer covering the sidewalls of openings in the resin layer, where conductive paste is filled within these openings to create a secure electrical connection between the semiconductor chip and the interconnect traces without penetrating into the adhesive resin.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If conductive paste is poured to fill the openings and the semiconductor chip is pressed against the interconnect substrate, then electrical connection between electrode terminals and interconnect layers is achieved, but conductive paste penetrates into the adhesive resin layer through the inner walls of the openings, resulting in reduced insulation between electrode terminals

Engineering Contradiction:
Improveelectrical connection reliabilityVSAvoidconductive paste penetration causing insulation reduction
Core Design Contradiction:
ReliabilityVSObject-affected harmful factors

Solution Approach 1:

A barrier layer is introduced as an intermediary component between the conductive paste and the adhesive resin layer. This barrier layer specifically prevents conductive paste from penetrating into the adhesive resin layer through the inner walls of openings, while allowing the conductive paste to maintain electrical connection with the electrode terminals. The barrier layer thus mediates between the need for electrical connectivity and the need for insulation preservation.

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The opening structure is segmented into distinct functional zones: an upper portion for electrical connection, a barrier layer portion for preventing paste penetration, and a lower portion for adhesive bonding. This segmentation allows each zone to perform its specific function independently, with the barrier layer specifically addressing the insulation issue without affecting the electrical connection functionality.

Inventive Principle:
Principle #1Segmentation

2Ease of operation

If the adhesive resin layer has openings for conductive paste, then electrical connection is enabled, but the openings provide pathways for conductive paste to penetrate into the adhesive resin layer, affecting insulation

Engineering Contradiction:
Improveelectrical connection easeVSAvoidinsulation reliability
Core Design Contradiction:
Ease of operationVSReliability

Solution Approach 1:

The barrier layer serves as a mediator within the opening structure, allowing the opening to maintain its function for electrical connection while preventing the harmful effect of conductive paste penetration. The barrier layer is positioned within the opening to selectively block paste migration while permitting electrical connectivity.

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The barrier layer is locally positioned only at the inner walls of the openings where paste penetration is a concern, rather than throughout the entire adhesive resin layer. This localized approach maintains the overall ease of electrical connection while providing targeted protection against insulation degradation.

Inventive Principle:
Principle #3Local quality

Data Source

PatentUS10593621B2Semiconductor device with barrier layer
Publication Date: 2020.03.17 SHINKO ELECTRIC IND CO LTD
  • US10593621B2 patent drawing
  • US10593621B2 patent drawing
  • US10593621B2 patent drawing

AI summary

A semiconductor device includes an interconnect substrate, an interconnect trace disposed on an upper surface of the interconnect substrate, a semiconductor chip mounted on the upper surface of the interconnect substrate, an adhesive resin layer disposed between the upper surface of the interconnect substrate and a lower surface of the semiconductor chip to bond the interconnect substrate and the semiconductor chip, the adhesive resin layer including an opening at a bottom of which an upper surface of the interconnect trace is situated, a barrier layer covering a sidewall of the opening, and conductive paste disposed inside the opening, wherein an electrode terminal of the semiconductor chip situated at the lower surface thereof is disposed inside the opening, with the conductive paste filling a space between the barrier layer and the electrode terminal.