Semiconductor Barrier Layer Segmentation for Planarization Integrity

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Solution Overview

Problem

Conventional semiconductor manufacturing processes face challenges in ensuring the adhesion of barrier layers to insulation layers during the planarization process, leading to incomplete filling of contact holes and increased electrical resistance due to the removal of the first tungsten layer, resulting in voids and electrical shorts.

Innovation Solution

A method involving the formation of a barrier layer with a residual metal layer at the bottom and sidewalls of contact holes, and a metal nitride layer on the upper sidewalls and insulation layer, using atomic layer deposition and plasma etching to prevent the removal of the barrier layer during planarization, ensuring complete filling and low contact resistance.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If a conventional deposition process is used to form metal wiring, then the metal layer can be deposited to sufficient thickness, but the aspect ratio of contact holes or via holes increases rapidly making it difficult to fill them completely

Engineering Contradiction:
Improvemetal layer thicknessVSAvoidcontact hole filling completeness
Core Design Contradiction:
Quantity of substanceVSManufacturing precision

Solution Approach 1:

The barrier layer is segmented into two distinct layers: a first barrier layer (tungsten) at the bottom and lower portion of sidewalls, and a second barrier layer (tungsten nitride) at the upper portion of sidewalls. This segmentation allows each layer to perform its specific function - the tungsten layer provides adhesion and reduces contact resistance, while the tungsten nitride layer provides etch resistance during planarization.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Different materials are used at different locations within the barrier layer structure. Tungsten is used at the bottom and lower sidewalls where adhesion and conductivity are critical, while tungsten nitride is used at the upper sidewalls where etch resistance during planarization is the primary requirement. This local quality differentiation resolves the contradiction between filling completeness and thickness control.

Inventive Principle:
Principle #3Local quality

2Ease of manufacture

If tungsten is used as the barrier layer material, then the deposition process is facilitated and electrical resistance is reduced, but the tungsten layer has difficulty adhering to the oxide insulation layer and source gases cause damage to the inner surface of contact holes

Engineering Contradiction:
Improvedeposition process easeVSAvoidbarrier layer adhesion and source gas resistance
Core Design Contradiction:
Ease of manufactureVSReliability

Solution Approach 1:

The barrier layer is divided into two functional segments: tungsten for adhesion and conductivity, and tungsten nitride for source gas resistance. This segmentation allows each material to optimize its performance for its specific function without compromise.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The barrier layer is formed as a composite structure combining tungsten and tungsten nitride. This composite approach leverages the advantageous properties of both materials - tungsten's excellent adhesion and low resistance, and tungsten nitride's resistance to source gases - to overcome the limitations of using either material alone.

Inventive Principle:
Principle #40Composite materials

3Reliability

If the barrier layer is formed with a first tungsten layer and a tungsten nitride layer, then adhesion and source gas resistance are improved, but the first tungsten layer is removed during the planarization process causing voids and electrical shorts

Engineering Contradiction:
Improvebarrier layer adhesion and source gas resistanceVSAvoidbarrier layer integrity after planarization
Core Design Contradiction:
ReliabilityVSManufacturing precision

Solution Approach 1:

The barrier layer is segmented into tungsten and tungsten nitride layers with the nitride layer positioned at the upper portion where it will provide etch resistance during planarization, preventing removal of the critical lower barrier layer.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The tungsten nitride layer is formed beforehand at the upper portion of the barrier layer to provide a protective cushion during the planarization process. This layer absorbs the etching action, shielding the underlying tungsten layer from being removed and preventing subsequent void formation and electrical shorts.

Inventive Principle:
Principle #11Beforehand cushioning (Prior cushioning)

4Reliability

If the anti-diffusion layer is formed to have minimal thickness, then contact resistance is reduced, but it becomes difficult to form uniformly on the inner surface of small contact holes or via holes

Engineering Contradiction:
Improvecontact resistanceVSAvoidanti-diffusion layer uniformity
Core Design Contradiction:
ReliabilityVSManufacturing precision

Solution Approach 1:

The barrier layer structure applies local quality by using tungsten nitride at the upper sidewalls where uniform coverage is critical for etch protection, while using tungsten at the bottom where conductivity is paramount. This spatial differentiation of material properties resolves the contradiction between thinness and uniformity.

Inventive Principle:
Principle #3Local quality

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach prevents the barrier layer from being removed during planarization, ensuring no gaps between the insulation layer and the metal plug, reducing contact resistance and preventing electrical shorts, thereby enhancing the reliability and performance of semiconductor devices.

Implementation Method 1

using atomic layer deposition and plasma etching to prevent the removal of the barrier layer during planarization

Methodology Applied
Scientific EffectAtomic layer deposition: Chemical Vapour Deposition

Implementation Method 2

using atomic layer deposition and plasma etching to prevent the removal of the barrier layer during planarization

Methodology Applied
Scientific EffectPlasma etching: Plasma

Data Source

PatentUS8466556B2Semiconductor device and method of manufacturing the same
Publication Date: 2013.06.18 SAMSUNG ELECTRONICS CO LTD
  • US8466556B2 patent drawing
  • US8466556B2 patent drawing
  • US8466556B2 patent drawing

AI summary

In a method of forming a wiring structure for a semiconductor device, an insulation layer is formed on a semiconductor substrate on which a plurality of conductive structures is positioned. An upper surface of the insulation layer is planarized and spaces between the conductive structures are filled with the insulation layer. The insulation layer is partially removed from the substrate to form at least one opening through which the substrate is partially exposed. A residual metal layer is formed on a bottom and a lower portion of the sidewall of the at least one opening and a metal nitride layer is formed on the residual metal layer and an upper sidewall of the opening with a metal material. Accordingly, an upper portion of the barrier layer can be prevented from being removed in a planarization process for forming the metal plug.