Semiconductor Barrier Layer Between Source Drain and Gate Spacers
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Solution Overview
Problem
In FinFET semiconductor devices, dopant diffusion and segregation into gate spacers reduce dopant concentration in source and drain regions, leading to increased external resistance and decreased charge carrier mobility, which affects the electrical performance of the transistors.
Innovation Solution
A semiconductor layer is conformally disposed between the source and drain regions and their corresponding gate spacers, preventing dopant diffusion and segregation, and reducing interfacial traps, thereby maintaining high dopant concentration and improving charge carrier mobility.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If dopant diffusion and segregation into gate spacers is allowed, then manufacturing process is simpler, but dopant concentration in source and drain regions decreases leading to increased external resistance
Solution Approach 1:
A semiconductor layer is introduced as an intermediary barrier between the source/drain regions and gate spacers. This intermediate layer prevents dopant diffusion and segregation into the gate spacers while maintaining the dopant concentration in the source and drain regions, thereby reducing external resistance without complicating the manufacturing process.
Solution Approach 2:
The structure is segmented by introducing a distinct semiconductor layer that separates the source/drain regions from the gate spacers. This segmentation creates a barrier that controls dopant distribution, preventing unwanted diffusion into the gate spacers while preserving the electrical properties of the source and drain regions.
2Ease of manufacture
If dopant diffusion into gate spacers occurs, then manufacturing process is simpler, but charge carrier mobility decreases
Solution Approach 1:
The semiconductor layer acts as a mediator that blocks dopant diffusion into the gate spacers. By preventing dopant segregation at the interface, the layer maintains high charge carrier mobility in the source and drain regions, improving device speed without adding manufacturing complexity.
Solution Approach 2:
The semiconductor layer is formed in advance to establish a protective barrier before dopant diffusion can occur. This preliminary action prevents dopant segregation at the critical interface between source/drain regions and gate spacers, preserving charge carrier mobility from the outset.
3Reliability
If semiconductor layer is added to prevent dopant diffusion, then external resistance decreases, but device complexity increases
Solution Approach 1:
The semiconductor layer is made compositionally similar to the surrounding semiconductor materials (e.g., using the same or similar semiconductor material for the layer, source/drain regions, and channel). This homogeneity allows the layer to function as a dopant diffusion barrier while maintaining material compatibility and minimizing structural complexity.
4Loss of energy
If semiconductor layer is added to prevent dopant diffusion, then energy efficiency increases, but manufacturing complexity increases
Solution Approach 1:
By using compositionally similar semiconductor materials for the barrier layer and surrounding structures, the patent minimizes manufacturing complexity while achieving the energy efficiency benefits of reduced external resistance and improved charge carrier mobility.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution reduces external resistance, enhances energy efficiency, and increases the response time of FinFET semiconductor devices by maintaining high dopant concentration and minimizing charge carrier traps at the interface.
Implementation Method 1
dopant diffusion and segregation into gate spacers reduce dopant concentration in source and drain regions
Data Source
AI summary
A semiconductor device is described that includes a first semiconductor layer conformally disposed on at least a portion of a source region and a second semiconductor layer conformally disposed on at least a portion of a drain region between the source/drain regions and corresponding gate spacers. The semiconductor layer can prevent diffusion and/or segregation of dopants from the source and drain regions into the gate spacers of the gate stack. Maintaining the intended location of dopant atoms in the source region and drain region improves the electrical characteristics of the semiconductor device including the external resistance (“Rext”) of the semiconductor device.