Semiconductor Barrier Layer for Threshold Voltage Uniformity
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
As semiconductor devices with decreasing feature sizes face challenges in maintaining threshold voltage uniformity and carrier mobility due to ion implantation depth and doped profile issues in MOSFETs, particularly in PMOS and NMOS structures, where dopants like boron can diffuse during fabrication processes.
Innovation Solution
A method is introduced to fabricate semiconductor devices by forming a barrier layer doped with carbon or nitrogen around the source/drain regions to control the doped profile and improve threshold voltage and saturation current uniformity, using epitaxial processes and specific doping concentrations to prevent dopant diffusion.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If feature size is decreased to increase IC density, then IC density is improved, but threshold voltage uniformity deteriorates due to ion implantation depth and doped profile issues
Solution Approach 1:
The patent introduces a barrier layer with specific dopant concentration (1E16 to 1E18 atoms/cm³) localized around the source/drain regions, creating a non-uniform dopant distribution that specifically addresses threshold voltage control in critical areas while maintaining overall device density
Solution Approach 2:
The barrier layer acts as an intermediary structure between the source/drain regions and the channel, mediating the dopant distribution to prevent excessive doping in the channel region while maintaining proper source/drain junction characteristics
2Productivity
If ion implantation is used to dope source/drain regions, then doping efficiency is improved, but dopant diffusion during fabrication processes worsens threshold voltage control
Solution Approach 1:
The barrier layer is formed before source/drain doping, preliminarily establishing a dopant concentration gradient that prevents excessive dopant diffusion into the channel region during subsequent fabrication processes
Solution Approach 2:
The patent changes the dopant concentration parameter in the barrier layer (1E16 to 1E18 atoms/cm³) to optimize the balance between preventing dopant diffusion and maintaining proper electrical characteristics
3Reliability
If selective grown SiGe is used to enhance carrier mobility, then MOSFET performance is improved, but implementation complexity increases in scaled devices
Solution Approach 1:
The patent applies selective doping to specific regions (source/drain areas with barrier layer) rather than uniformly across the entire device, locally enhancing carrier mobility where needed while simplifying the overall implementation in scaled devices
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The approach enhances the threshold voltage and saturation current uniformity by effectively controlling the doped profile, reducing dopant diffusion and improving carrier mobility in MOSFETs, thereby addressing the challenges associated with shrinking feature sizes.
Implementation Method 1
A barrier layer is formed in a source/drain recess cavity... The barrier layer has a dopant concentration gradient... to control the doped profile and improve threshold voltage and saturation current uniformity, using epitaxial processes and specific doping concentrations to prevent dopant diffusion
Implementation Method 2
A barrier layer is formed in a source/drain recess cavity by an epitaxial process... The barrier layer has a dopant concentration gradient
Data Source
AI summary
A method of fabricating a semiconductor device includes following steps. A trench is formed in a substrate. A barrier layer and an epitaxy layer are formed in sequence in the trench. The barrier layer has a first dopant. A source/drain recess cavity is formed by etching at least the epitaxial layer. A source/drain region is formed in the source/drain recess cavity. The source/drain region has a second dopant.