Semiconductor Barrier Layers for Leakage Reduction
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Solution Overview
Problem
Conventional semiconductor structures face challenges in reducing the short channel effect and leakage current due to the difficulty in adjusting the thickness of the dummy gate dielectric layer and operation voltage, leading to increased junction capacitance and leakage issues, especially in NMOS devices.
Innovation Solution
A semiconductor structure and fabrication method involving the formation of first and second barrier layers by ion implantation processes to prevent the diffusion of source/drain doping ions into the channel region, using barrier ions with opposite conductivity types to recombine with source/drain ions and reduce the short channel effect, while maintaining a thin halo region to minimize threshold voltage increase.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If ultra shallow junction (USJ) technology is used to reduce the short channel effect, then the short channel effect is reduced, but the transistor develops junction capacitance issues and junction leakage issues in the drain region
Solution Approach 1:
A barrier layer is introduced as an intermediary between the source/drain doping ions and the channel region. This barrier layer, formed by implanting barrier ions (such as carbon, nitrogen, or oxygen ions) into the semiconductor substrate, acts as a mediator that prevents direct interaction between the source/drain ions and the channel, thereby eliminating junction capacitance and junction leakage issues while maintaining the short channel effect reduction benefits of USJ technology
Solution Approach 2:
The harmful junction capacitance and junction leakage effects are extracted or removed from the system by introducing the barrier layer. The barrier layer effectively separates the source/drain regions from the channel region, taking out the problematic direct junction interface that causes capacitance and leakage, while preserving the essential USJ structure for short channel effect control
2Productivity
If the thickness of the dummy gate dielectric layer is reduced to accommodate smaller transistor sizes, then more transistors can be disposed in one chip, but the short channel effect becomes more difficult to reduce and leakage current increases
Solution Approach 1:
The barrier layer serves as an intermediary that enables the use of thinner dummy gate dielectric layers for higher integration density while preventing the associated short channel effect and leakage current problems. By placing the barrier layer at the interface between the source/drain regions and the channel region, it mediates the interaction and prevents harmful effects even when the gate dielectric layer is thin
Solution Approach 2:
The barrier layer introduces local quality changes at the source/drain to channel interface by implanting specific barrier ions (carbon, nitrogen, or oxygen) that create a region with different electrical properties. This localized modification at the critical interface region allows the overall device to achieve better short channel effect control and reduced leakage current while maintaining thin gate dielectric for high density
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The method effectively reduces the short channel effect and leakage current by controlling the diffusion of source/drain ions, improving the performance of semiconductor devices without significantly increasing the leakage current in the drain region.
Implementation Method 1
performing one or more of a first ion implantation process, for implanting first barrier ions in the base substrate toward the source region to form a first barrier layer under the opening, and a second ion implantation process, for implanting second barrier ions in the base substrate toward the source region to form a second barrier layer under the opening
Implementation Method 2
barrier ions with opposite conductivity types to recombine with source/drain ions and reduce the short channel effect
Data Source
AI summary
Semiconductor structures and fabrication methods thereof are provided. An exemplary fabrication method includes providing a base substrate; forming a dummy gate structure over the base substrate; forming source/drain regions having source/drain doping ions in the base substrate at both sides of the dummy gate structure; forming a dielectric layer on the source/drain regions and covering the side surfaces of the dummy gate structure; removing the dummy gate structure to form an opening in the dielectric layer; performing one or more of a first ion implantation process, for implanting first barrier ions in the base substrate toward the source region to form a first barrier layer under the opening, and a second ion implantation process, for implanting second barrier ions in the base substrate toward the source region to form a second barrier layer under the opening; and forming a gate structure in the opening.