Semiconductor Barrier Region for Junction Leakage Reduction

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Solution Overview

Problem

Charge leakage across PN junctions at the cut edges of semiconductor dies can occur due to damage during the singulation process, affecting the performance of imager devices and other electronic circuits.

Innovation Solution

A doped barrier region is formed between the cut edge and semiconductor devices to isolate them from leakage pathways, using a heavily doped n-type region that extends from the surface to below the PN junction, creating additional diodes to prevent current leakage.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If the wafer is cut at the scribe line to singulate each die, then each die can be separated and used individually, but damage occurs at the cut edges creating leakage pathways across the PN junction

Engineering Contradiction:
Improvedie singulationVSAvoidcharge leakage
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

An isolation structure is formed at the cut edge before the wafer is singulated into individual dies. This preliminary formation of the isolation structure prevents damage to the PN junction during the cutting process, thereby preventing leakage pathways while still allowing die singulation to proceed.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

An isolation structure acts as an intermediary element between the cut edge and the PN junction. This isolation structure absorbs or blocks the damage that would otherwise occur at the PN junction during cutting, preventing charge leakage while maintaining the ability to singulate dies.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Ease of manufacture

If no isolation structure is used at the cut edge, then the manufacturing process is simpler, but charge leakage pathways form across the PN junction affecting device performance

Engineering Contradiction:
Improveprocess simplicityVSAvoiddevice performance
Core Design Contradiction:
Ease of manufactureVSReliability

Solution Approach 1:

The isolation structure segments or divides the continuous PN junction at the cut edge into isolated regions. By creating this segmentation before singulation, the structure prevents leakage pathways from forming across the entire junction, thereby maintaining device performance without significantly complicating the manufacturing process.

Inventive Principle:
Principle #1Segmentation

3Device complexity

If the PN junction is left exposed at the cut edge, then fewer manufacturing steps are required, but leakage pathways adversely affect imager device performance

Engineering Contradiction:
Improvestructure complexityVSAvoidcharge leakage
Core Design Contradiction:
Device complexityVSObject-affected harmful factors

Solution Approach 1:

The isolation structure extracts or removes the harmful effect of charge leakage by creating a protective barrier at the cut edge. This structure takes out the vulnerability of the exposed PN junction before singulation, preventing leakage pathways from forming and adversely affecting imager device performance.

Inventive Principle:
Principle #2Taking out (Extraction)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The barrier region effectively isolates leakage pathways, enhancing the electrical isolation and performance of semiconductor devices by preventing charge leakage across the PN junctions at the cut edges.

Implementation Method 1

A doped barrier region is formed between the cut edge and semiconductor devices to isolate them from leakage pathways, using a heavily doped n-type region that extends from the surface to below the PN junction, creating additional diodes to prevent current leakage.

Methodology Applied
Scientific EffectPN junction diode effect: Diode

Data Source

PatentUS8633513B2Structures and methods for reducing junction leakage in semiconductor devices
Publication Date: 2014.01.21 APTINA IMAGING CORP
  • US8633513B2 patent drawing
  • US8633513B2 patent drawing
  • US8633513B2 patent drawing

AI summary

Structures and method for reducing junction leakage in semiconductor devices. The die can include a substrate having a cut edge, a first region of first conductivity type within the substrate and a region of a second conductivity type within the substrate and in contact with the first region forming a junction. At least one semiconductor device is on the substrate. A second region of the first conductivity type is between the plurality of semiconductor devices and the cut edge within the region of the second conductivity type, and extending to the junction. The second region of the first conductivity type can isolate the at least one semiconductor device from leakage pathways created by saw damage at the junction along the cut edge.