Semiconductor Package Barrier Member Prevents Sealant Delamination
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Solution Overview
Problem
Conventional semiconductor packages face challenges in maintaining structural stability and accurate dimensions due to the sealing process, which can lead to delamination of the electrode pad and lead wire from the substrate, affecting the reliability and mechanical strength of the package.
Innovation Solution
The semiconductor package design incorporates a barrier member that surrounds the semiconductor chip and lead wire, creating a controlled space for the sealing member, which enhances mechanical strength and prevents delamination by ensuring accurate dimensions and improved binding forces.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a sealing member is used to protect the semiconductor chip, then the chip is protected from external environment, but the structural stability and dimensions of the package are compromised due to delamination
Solution Approach 1:
The package structure is segmented into distinct functional zones: a first bonding member for chip mounting, a second bonding member forming a ring structure, and a barrier member creating a groove. This segmentation allows the sealing member to be confined to a specific region, preventing it from causing delamination while maintaining protection functionality.
Solution Approach 2:
The barrier member acts as an intermediary element between the bonding members and the sealing member. It creates a physical boundary (groove) that mediates the interaction between these components, preventing direct contact between the sealing member and the bonding members that would cause delamination.
2Reliability
If the sealing member is applied to seal the chip and wire, then protection is provided, but delamination of electrode pad and lead wire occurs affecting mechanical strength
Solution Approach 1:
The bonding members are segmented into functional zones with the second bonding member forming a ring structure that creates a groove. This segmentation confines the sealing member to a specific area, preventing it from interfering with the bonding between electrode pads and substrate, thereby maintaining mechanical strength.
Solution Approach 2:
The barrier member serves as an intermediary that creates a physical boundary, preventing the sealing member from directly contacting and delaminating the electrode pads and lead wires, thus preserving mechanical strength while maintaining sealing protection.
3Reliability
If conventional sealing process is used, then the chip is sealed, but accurate dimensions and structural stability are not maintained
Solution Approach 1:
The package is segmented into distinct regions defined by the barrier member and bonding members. This segmentation creates well-defined boundaries that constrain the sealing member, ensuring accurate dimensions and consistent package geometry while maintaining the sealing function.
Solution Approach 2:
The barrier member acts as an intermediary that defines precise boundaries for the sealing member placement. This intermediary structure ensures that the sealing process occurs within controlled dimensions, improving manufacturing precision while maintaining sealing effectiveness.
Data Source
AI summary
A semiconductor package can include a semiconductor chip on a substrate inside the semiconductor package and an electrode pad spaced apart from the semiconductor chip on the substrate inside the semiconductor package. A wire can be inside the semiconductor package, to connect the electrode pad to the semiconductor chip and a barrier member can be on the substrate fencing-in the semiconductor chip, where the electrode pad and the wire can be in an interior portion of the substrate. A sealing material can be in the interior portion of the substrate fenced-in by the barrier member, where the sealing material covering the semiconductor chip, the electrode pad, and the wire.