Semiconductor Barrier Layer Overhangs Prevent Erosion
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Solution Overview
Problem
Conventional semiconductor device manufacturing processes, such as trench-filling, suffer from erosion and recesses due to multiple planarization and cleaning steps, leading to undesirable electrical characteristics and gate height loss.
Innovation Solution
A method involving the formation of a substrate with trenches, a barrier layer with overhung portions, and a seed layer, where the upper portions are selectively removed to allow conductive material deposition, ensuring aligned top surfaces and preventing erosion and dishing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If multiple CMP polishing processes are used to planarize the structure, then the surface flatness is improved, but the gate height is reduced due to erosion and recesses
Solution Approach 1:
The method performs preliminary planarization only at the critical moment before conductor deposition, rather than multiple times during the process. The barrier layer and seed layer are formed with controlled thicknesses that anticipate the final planarization needs, allowing a single CMP step to achieve both flatness and height preservation
Solution Approach 2:
The invention changes the thickness parameters of the barrier layer and seed layer to optimize the single CMP planarization step. By carefully controlling these layer thicknesses before the final planarization, the process achieves surface flatness while preserving gate height, eliminating the need for multiple polishing steps that cause erosion
2Reliability
If multiple cleaning treatments are applied to the structure, then the cleanliness is improved, but the gate height is further reduced and dishing profile is caused
Solution Approach 1:
The invention extracts and eliminates unnecessary cleaning treatments from the process flow. By redesigning the barrier layer and seed layer formation process, the method achieves sufficient cleanliness without requiring multiple cleaning steps, thereby preventing gate height loss and dishing profile formation
Solution Approach 2:
The barrier layer and seed layer are designed as sacrificial elements that protect the underlying structure during a single critical cleaning step. These layers are intentionally formed with specific thicknesses to withstand one cleaning treatment while maintaining gate height, after which they are removed or integrated into the final structure
3Strength
If the barrier layer and seed layer are formed thick to prevent erosion, then the protection is improved, but the final conductor profile completeness is reduced
Solution Approach 1:
The invention optimizes the thickness parameters of the barrier layer and seed layer to achieve the right balance. Rather than making them excessively thick for protection, the method calculates precise thickness values that provide sufficient erosion resistance while ensuring that after single CMP planarization, the conductor profile remains complete and flaw-free
Solution Approach 2:
The barrier layer and seed layer are formed with preliminary thickness control that anticipates the single CMP planarization step. Their thickness is pre-calculated to provide necessary protection during processing while ensuring that after planarization, the conductor achieves the desired complete profile without excess material causing defects
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method enables the creation of semiconductor devices with conductive contacts of sufficient height and complete profiles, improving electrical properties by avoiding gate height loss and defects like erosion and dishing.
Implementation Method 1
a barrier layer is formed on an upper surface of the insulation and in sidewalls of the trenches
Implementation Method 2
A seed layer is formed on the barrier layer
Data Source
AI summary
A method for manufacturing a semiconductor device is provided. A substrate with an insulation formed thereon is provided, wherein the insulation has plural trenches, and the adjacent trenches are spaced apart from each other. A barrier layer is formed on an upper surface of the insulation and in sidewalls of the trenches, and the barrier layer comprises overhung portions corresponding to the trenches. A seed layer is formed on the barrier layer. Then, an upper portion of the seed layer formed on an upper surface of the barrier layer is removed. An upper portion of the barrier layer is removed for exposing the upper surface of the insulation. Afterwards, the conductors are deposited along the seed layer for filling up the trenches, wherein the top surfaces of the conductors are substantially aligned with the upper surface of the insulation.