3D Semiconductor Barrier Pattern Protection

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Solution Overview

Problem

The process of replacing sacrificial layers with conductive patterns in 3D semiconductor devices often results in damaged conductive patterns, leading to increased process errors and reduced semiconductor device performance.

Innovation Solution

The semiconductor device includes interlayer dielectrics with a channel layer and line pattern regions, where a barrier pattern is formed along the surface of the line pattern regions and a reaction preventing pattern is added to prevent the barrier pattern from reacting with the protection pattern, ensuring the barrier pattern's thickness and preventing damage during the metal deposition process.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If sacrificial layers are replaced with conductive patterns in the conventional manner, then the 3D semiconductor device structure is formed, but the conductive patterns become damaged during the replacement process

Engineering Contradiction:
Improvedevice fabrication efficiencyVSAvoidconductive pattern integrity
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

A barrier pattern is introduced as an intermediary layer between the sacrificial layer and the conductive pattern. This barrier pattern prevents direct contact and potential damage during the replacement process, while still allowing the structural transformation to occur. The barrier layer acts as a protective mediator that preserves conductive pattern integrity throughout the fabrication process.

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The barrier pattern is formed in advance before the conductive pattern replacement process. This preliminary protective layer is prepared on the sacrificial layer surface, ensuring that when the conductive pattern is subsequently formed or replaced, the underlying structure is already protected and ready to prevent damage.

Inventive Principle:
Principle #10Preliminary action

2Reliability

If the barrier pattern is formed to protect the conductive pattern, then the conductive pattern integrity is improved, but the manufacturing process complexity increases

Engineering Contradiction:
Improveconductive pattern integrityVSAvoidmanufacturing process complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The barrier pattern is applied selectively only in regions where conductive patterns will be formed, rather than uniformly across the entire substrate. This localized approach provides protection exactly where needed during the replacement process, while minimizing the overall complexity and material usage of the manufacturing process.

Inventive Principle:
Principle #3Local quality

3Reliability

If the barrier pattern thickness is maintained to prevent damage, then the protective function is improved, but the reaction with protection pattern causes thickness reduction

Engineering Contradiction:
Improvebarrier pattern protective functionVSAvoidbarrier pattern thickness
Core Design Contradiction:
ReliabilityVSLoss of substance

Solution Approach 1:

A reaction preventing pattern is introduced to counteract the harmful chemical reaction between the barrier pattern and the protection pattern. This preliminary protective measure prevents the oxidation reaction that would otherwise reduce the barrier pattern thickness, ensuring the protective function is maintained throughout the fabrication process.

Inventive Principle:
Principle #9Preliminary anti-action

Solution Approach 2:

The reaction preventing pattern acts as an intermediary barrier between the barrier pattern and the protection pattern. This intermediate layer prevents direct contact and chemical reaction between the two patterns, preserving the barrier pattern's thickness and protective capabilities while still allowing the protection pattern to fulfill its function.

Inventive Principle:
Principle #24Intermediary (Mediator)

Data Source

PatentUS9754962B2Three-dimensional (3D) semiconductor device
Publication Date: 2017.09.05 SK HYNIX INC
  • US9754962B2 patent drawing
  • US9754962B2 patent drawing
  • US9754962B2 patent drawing

AI summary

A semiconductor device includes interlayer dielectrics stacked and spaced apart from each other, a channel layer passing through the interlayer dielectrics, line pattern regions each surrounding a sidewall of the channel layer to be disposed between the interlayer dielectrics, a barrier pattern formed along a surface of each of the line pattern regions and the sidewall of the channel layer, a reaction preventing pattern formed on the barrier pattern along a surface of a first region of each of the line pattern regions, the first region being adjacent to the channel layer, a protection pattern filled in the first region on the reaction preventing pattern, and a first metal layer filled in a second region of each of the line pattern regions.