Semiconductor Barrier Prevents Storage Node Contact Bridges
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Solution Overview
Problem
The 6F2 semiconductor structure faces challenges in preventing bridges between storage node contacts (SNCs) due to excessive etching of the insulation film below the bit line, which reduces productivity and increases the risk of electrical shorts during the manufacturing process of high-capacity dynamic random access memory (DRAM) devices.
Innovation Solution
A semiconductor device structure that includes a barrier formed below the bit line between bit line contacts, with a smaller critical dimension than the bit line, made of the same material as the contact spacer, and having a lower etch selectivity ratio than the interlayer insulation film, which prevents bridges between SNCs by electrically insulating adjacent storage node contacts and serving as an etch stop during the etching process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If additional etching is performed to increase contact region size, then contact region between storage node and active region is increased, but insulation film below bit line is excessively etched causing bridge between SNCs
Solution Approach 1:
The patent divides the bit line structure into segmented portions by forming barriers between adjacent bit line contacts. These barriers segment the continuous insulation film into isolated regions, preventing lateral etching from connecting adjacent storage node contacts while preserving vertical etching access for contact formation.
Solution Approach 2:
The barrier structure is formed in advance before the storage node contact formation process. This preliminary action creates a protective framework that prevents excessive lateral etching of the insulation film during subsequent processing steps, ensuring that the contact region can be adequately formed without causing bridges between SNCs.
2Quantity of substance
If chip size is increased to accommodate additional memory, then memory capacity is increased, but number of chips per wafer is reduced lowering productivity
Solution Approach 1:
The patent applies local quality by implementing the barrier structure specifically in regions where bit line contacts are formed, rather than uniformly across the entire chip. This localized approach enables tighter spacing of storage node contacts in critical areas while maintaining overall chip layout flexibility, allowing higher density without sacrificing yield.
Solution Approach 2:
The patent changes the critical dimension parameter of the barrier to be smaller than that of the bit line. This parameter change enables the barrier to occupy minimal space while still providing effective separation, allowing closer spacing of adjacent structures and increasing the number of memory cells that can be packed into each chip.
3Productivity
If barrier critical dimension is reduced to increase density, then more structures can be packed, but manufacturing precision requirements increase
Solution Approach 1:
The barrier acts as an intermediary structure between the bit line contacts and the storage node contacts. By positioning this intermediate element with a smaller critical dimension, the patent enables precise spatial separation without requiring the main bit line and contact structures to be manufactured with extremely tight tolerances. The intermediary barrier absorbs the precision requirements, protecting the larger, easier-to-manufacture structures.
Data Source
AI summary
A barrier for preventing a bridge between adjacent storage node contacts is formed below a bit line located between the bit line contacts, so that a contact region between each storage node contact and an active region is increased in size. The semiconductor device includes a device isolation film defining an active region, a bit line contact coupling the active region to a bit line, and a barrier formed below the bit line located between the bit line contacts.