Semiconductor Base Region Multi-Peak Doping Profile
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Solution Overview
Problem
The existing semiconductor devices with a carrier accumulation layer face a reduction in on-resistance due to impurity diffusion during the formation of the base region, which inhibits the sufficient accumulation of holes in the drift region, leading to increased on-resistance.
Innovation Solution
The semiconductor device is manufactured by forming a base region with an impurity concentration profile having multiple peaks along the film thickness direction through multiple doping processes, which reduces the base annealing time and minimizes impurity diffusion in the carrier accumulation layer, thereby maintaining higher impurity concentration and reducing on-resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the base region is formed after forming the carrier accumulation layer, then the base region can be properly created, but the impurity in the carrier accumulation layer diffuses during base region formation, reducing its impurity concentration
Solution Approach 1:
The carrier accumulation layer is formed by doping impurity before the base region formation process. By performing this doping action in advance, the carrier accumulation layer is established with the required impurity concentration profile before any diffusion can occur during subsequent base region processing.
Solution Approach 2:
The patent employs multiple doping processes with different impurity concentrations and depth profiles to create a complex impurity concentration profile in the carrier accumulation layer. This includes forming peaks at different depths, which maintains higher overall impurity concentration despite the diffusion that occurs during base region formation.
2Reliability
If the impurity concentration of the carrier accumulation layer is reduced due to diffusion, then the base region can be formed, but the on-resistance cannot be sufficiently reduced due to insufficient hole accumulation in the drift region
Solution Approach 1:
The patent creates a multi-peaked impurity concentration profile in the carrier accumulation layer through multiple doping processes. This complex profile maintains sufficiently high impurity concentration to generate adequate hole accumulation in the drift region, thereby achieving low on-resistance while still allowing base region formation.
Solution Approach 2:
The carrier accumulation layer is created with a composite impurity profile containing multiple peaks at different depths, rather than a uniform concentration. This composite structure provides both the necessary impurity concentration for hole accumulation and compatibility with subsequent base region formation.
3Loss of time
If multiple doping processes are used to form the base region with multiple impurity peaks, then the base annealing time can be reduced, but the process complexity increases
Solution Approach 1:
The base region formation is divided into multiple doping processes, each creating a specific impurity peak at a different depth. This segmentation allows each doping step to be optimized independently and reduces the total annealing time required compared to forming a uniform base region in a single step.
Solution Approach 2:
The multiple doping processes are performed in advance of the base annealing step. By pre-establishing the multi-peaked impurity profile through sequential doping, the subsequent annealing time is minimized since the impurity distribution is already largely established before thermal diffusion begins.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for a shorter base annealing time, suppresses the reduction in impurity concentration of the carrier accumulation layer, and achieves lower on-resistance while maintaining a higher impurity concentration, enhancing the semiconductor device's performance and design margins.
Implementation Method 1
doping an impurity from one principal surface of a first semiconductor region of a first conductivity type and forming a second semiconductor region of the first conductivity type with a higher impurity concentration than an impurity concentration of the first semiconductor region
Implementation Method 2
the impurity in the carrier accumulation layer is also diffused during formation of the base region after forming the carrier accumulation layer
Data Source
AI summary
A semiconductor device according to one or more embodiments may include a first semiconductor region of a first conductivity type, a second semiconductor region of the first conductivity type with a higher impurity concentration than an impurity concentration of the first semiconductor region, the second semiconductor region being provided on a first principal surface of the first semiconductor region, a third semiconductor region of a second conductivity type provided on an upper surface of the second semiconductor region, the third semiconductor region being doped with an impurity in accordance with an impurity concentration profile including peaks along a film thickness direction, a fourth semiconductor region of the first conductivity type provided on an upper surface of the third semiconductor region.