Semiconductor Butted Contact Interconnect Etch-Back for Void Control
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Solution Overview
Problem
The formation of voids in interconnect structures during the dual damascene process can lead to increased contact resistance and device failures in semiconductor devices due to differing deposition rates of metals and varying heights of interconnect structures, resulting in incomplete filling and open circuits.
Innovation Solution
A technique is implemented where a first interconnect structure is etched back to a depth near the starting depth of a second interconnect structure, allowing both structures to be filled in a single deposition operation, reducing the likelihood of void formation and improving filling efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a via and trench are filled with conductive material in the same deposition operation, then manufacturing efficiency is improved, but voids form due to differing deposition rates and varying heights resulting in incomplete filling
Solution Approach 1:
The patent applies preliminary action by performing an etch-back operation on the via structure before the final filling step. This removes excess conductive material from the via that would otherwise prevent complete filling when both via and trench are filled simultaneously. The etch-back step prepares the via structure in advance to accommodate the simultaneous filling process without void formation.
Solution Approach 2:
The patent changes the deposition parameters by using different deposition rates for the via and trench filling processes. The via is filled at a slower deposition rate compared to the trench, allowing the via to be completely filled even though both structures are filled in the same deposition operation. This parameter adjustment resolves the contradiction between manufacturing efficiency and filling completeness.
2Adaptability or versatility
If via and trench are etched using via-first or trench-first procedure, then process flexibility is improved, but contact resistance increases due to void formation
Solution Approach 1:
The etch-back step serves as a preliminary action that eliminates voids formed during the dual damascene process. By removing excess material from the via after initial filling but before final encapsulation, the process ensures low contact resistance while maintaining the flexibility to use either via-first or trench-first etching procedures.
3Manufacturing precision
If different deposition rates are used for via and trench, then filling completeness is improved, but process complexity increases
Solution Approach 1:
The etch-back operation acts as a preliminary corrective step that simplifies the overall process. Instead of requiring complex real-time deposition rate adjustments and monitoring, the process uses a straightforward etch-back step followed by encapsulation, achieving complete via filling without excessive process complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach minimizes defects, reduces contact resistance, enhances semiconductor device performance, decreases interconnect failures, and increases manufacturing yield and quality by ensuring complete filling of interconnect structures.
Implementation Method 1
the trench and the via are filled with a conductive material in the same deposition operation (e.g., electroplating)
Data Source
AI summary
A first interconnect structure (e.g., a gate interconnect) of a butted contact (BCT) is etched and filled. The first interconnect structure is then etched back such that a portion of the first interconnect structure is removed, then a second interconnect structure and the remaining portion of the first interconnect structure are filled. In this way, the height of the remaining portion of the first interconnect structure that is to be filled is closer to the height of the second interconnect structure when the second interconnect structure is filled relative to fully filling the second interconnect structure and fully filling the first interconnect structure in a single deposition operation. This reduces the likelihood that filling the second interconnect structure will close the first interconnect structure before the first interconnect structure can be fully filled, which may otherwise result in the formation of a void in the first interconnect structure.