Semiconductor BEOL Spacer Patterning for ¼ Pitch Conductive Lines
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Solution Overview
Problem
As semiconductor devices continue to integrate more components into smaller areas, manufacturing processes become increasingly challenging due to the need for precise patterning of conductive lines and vias, particularly in the back-end-of-line (BEOL) processes, where current methods are inefficient and costly.
Innovation Solution
A novel semiconductor device manufacturing method involving multiple step patterning using sacrificial material layers, photoresist, and spacer materials formed in-situ within an etching chamber, where [C(n)H(2n+2)+N2] plasma is used to create spacers that allow for trench formation and conductive line creation with reduced feature size and increased throughput.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional multi-step patterning processes are used for BEOL interconnects, then manufacturing precision can be maintained, but device complexity and manufacturing cost increase significantly
Solution Approach 1:
The patent segments the patterning process into distinct functional layers: a sacrificial material layer that defines the trench pattern, and a separate spacer material layer that forms the conductive line pattern. This segmentation allows each layer to be optimized independently and simplifies the overall process by enabling single-step lithography for both patterns.
Solution Approach 2:
The sacrificial material layer acts as an intermediary that temporarily holds the trench pattern during processing. It mediates between the lithography step and the final conductive line formation, allowing the spacer material to conformally deposit around it and transfer the pattern without requiring direct lithographic patterning of the conductive lines.
2Area of moving object
If feature sizes are reduced to increase integration density, then more components can be integrated, but manufacturing precision requirements become more stringent and difficult to achieve
Solution Approach 1:
The spacer material layer self-organizes around the sacrificial material through conformal deposition, automatically creating uniformly spaced conductive lines. This self-service mechanism eliminates the need for additional lithography alignment steps and ensures precise feature dimensions are achieved through the deposition process itself rather than requiring ultra-precise lithographic patterning.
3Manufacturing precision
If multiple lithography processes are used to form conductive lines, then patterning precision can be maintained, but manufacturing throughput decreases
Solution Approach 1:
The patent merges the trench patterning and conductive line patterning into a single lithography step by using the sacrificial material layer to define both patterns simultaneously. The spacer material then conformally deposits to transfer this single pattern into the final conductive line structure, eliminating multiple sequential lithography processes and significantly improving throughput.
4Ease of manufacture
If conventional spacer formation methods are used, then process simplicity can be maintained, but conformality of spacer deposition deteriorates
Solution Approach 1:
The patent transitions from planar spacer deposition to three-dimensional conformal deposition around vertical sidewalls of the sacrificial material. This dimensional change allows the spacer to form uniformly thick layers that wrap around complex geometries, achieving superior conformality while maintaining process simplicity through standard atomic layer deposition or chemical vapor deposition techniques.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method enables the formation of conductive lines with a ¼ pitch using a single lithography process, lowers manufacturing costs, and increases throughput by performing spacer formation and etching in a single chamber, improving the conformality and reducing the complexity of the manufacturing process.
Implementation Method 1
first spacers are formed on sidewalls of the patterned material layer... second spacers are formed on sidewalls of the patterned second material layer
Data Source
AI summary
Methods of manufacturing semiconductor devices are disclosed. In one embodiment, a material layer is formed over a workpiece. The workpiece includes a first portion, a second portion, and a hard mask disposed between the first portion and the second portion. The material layer is patterned, and first spacers are formed on sidewalls of the patterned material layer. The patterned material layer is removed, and the second portion of the workpiece is patterned using the first spacers as an etch mask. The first spacers are removed, and second spacers are formed on sidewalls of the patterned second portion of the workpiece. The patterned second portion of the workpiece is removed, and the hard mask of the workpiece is patterned using the second spacers as an etch mask. The first portion of the workpiece is patterned using the hard mask as an etch mask.