Semiconductor Structure BEVA Surface Roughness Mitigation
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Solution Overview
Problem
Conventional methods for forming a bottom electrode via (BEVA) in semiconductor structures result in surface roughness issues due to non-uniform lattice density and seam formation, leading to degraded performance of magnetic tunneling junction (MTJ) devices in MRAM cells.
Innovation Solution
The use of an electroplating operation to fill the BEVA hole with copper, followed by a multi-stage chemical mechanical polishing (CMP) process, and the application of a recap layer to achieve a smooth surface and eliminate stair profiles, thereby improving the surface roughness and film flatness.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional methods are used to form BEVA, then the manufacturing process is simple, but surface roughness increases and film flatness deteriorates
Solution Approach 1:
The manufacturing process is divided into multiple stages: initial BEVA formation, first CMP planarization, second CMP planarization, and recap layer formation. Each stage addresses specific surface irregularities progressively, transforming a single complex high-precision step into multiple manageable stages that collectively achieve superior surface roughness and film flatness
Solution Approach 2:
The recap layer is formed in advance over the BEVA structure before subsequent MTJ layer deposition. This preliminary action creates a pre-smoothed surface that ensures optimal film growth conditions for the MTJ device, preventing surface roughness from propagating to critical functional layers
2Reliability
If conventional BEVA formation is used, then the process is fast, but seam formation occurs and MTJ performance degrades
Solution Approach 1:
The patent converts the potentially harmful seam formations and surface irregularities created during BEVA formation into beneficial outcomes by using them as targets for selective removal in subsequent CMP stages. The multi-stage CMP process specifically addresses and eliminates these defects, transforming initial manufacturing challenges into opportunities for achieving superior surface quality and enhanced MTJ device performance
Solution Approach 2:
The manufacturing process employs parameter changes across different stages, including varying CMP polishing conditions, copper filling parameters, and recap layer deposition conditions. By adjusting these parameters at each stage, the process optimizes surface quality progressively while managing overall manufacturing efficiency
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the performance of MRAM cells by reducing surface roughness and ensuring optimal film growth, leading to improved memory performance and reliability.
Implementation Method 1
The BEVA includes a lining layer over a bottom and a sidewall of a trench of the BEVA, and electroplated copper over the lining layer, filling the trench of the BEVA
Implementation Method 2
followed by a multi-stage chemical mechanical polishing (CMP) process
Data Source
AI summary
The present disclosure provides a semiconductor structure. The semiconductor structure includes a bottom electrode via (BEVA) in a dielectric layer, a recap layer on the BEVA, a bottom electrode on the recap layer, and a magnetic tunneling junction (MTJ) layer over the recap layer and vertically aligning with the BEVA. The BEVA includes a lining layer over a bottom and a sidewall of a trench of the BEVA and a copper layer over the lining layer, filling the trench of the BEVA. The copper layer has a dimpled structure with a top surface lower than a top surface of the dielectric layer. The recap layer overlaps a top surface of the lining layer, an entire top surface of the copper layer, and a portion of the dielectric stack adjacent to the lining layer.