Semiconductor Package Interconnects for Blocking Bi Diffusion

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Solution Overview

Problem

The use of tin-bismuth (Sn-Bi) based low temperature soldering paste in semiconductor packaging leads to bi diffusion into SAC solder balls, causing interface cracks and reliability issues during surface mounting technology (SMT), as the bi material rises and forms intermetallic compounds, affecting board level reliability.

Innovation Solution

The semiconductor package design features connection members with a flat bottom surface and decreasing diameter side surface, along with an under-bump structure, oxide layer, or barrier layer to prevent bi diffusion and control solder paste flow, ensuring reliable bonding and reducing brittleness.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Temperature

If low temperature soldering paste using Sn-Bi-based materials is used for SMT bonding, then bonding temperature is reduced and cost is reduced, but Bi diffuses to the edge of SAC solder ball causing interface cracks and reliability deterioration

Engineering Contradiction:
Improvebonding temperatureVSAvoidboard level reliability
Core Design Contradiction:
TemperatureVSReliability

Solution Approach 1:

The patent introduces a barrier layer as an intermediary substance between the Sn-Bi solder paste and the SAC solder ball. This barrier layer prevents Bi diffusion while allowing the low temperature bonding process to proceed, thus resolving the contradiction between reduced bonding temperature and maintained reliability

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The patent extracts the harmful Bi component from the bonding interface by using a barrier layer that selectively blocks Bi diffusion. This allows the beneficial low temperature bonding to continue while removing the harmful diffusion effect

Inventive Principle:
Principle #2Taking out (Extraction)

2Ease of manufacture

If Bi in low temperature soldering paste rises to the edge of SAC solder ball, then Inter Metallic Compound (IMC) is formed, but cracks occur at the interface between metal pad and SAC solder ball

Engineering Contradiction:
Improvebonding processVSAvoidinterface strength
Core Design Contradiction:
Ease of manufactureVSStrength

Solution Approach 1:

The barrier layer acts as a mediator that prevents direct contact between Bi and the SAC solder ball edge, thereby preventing IMC formation and subsequent cracking while maintaining the bonding process

Inventive Principle:
Principle #24Intermediary (Mediator)

3Reliability

If connection members have flat bottom surface and decreasing diameter side surface, then Bi diffusion is prevented, but manufacturing complexity increases

Engineering Contradiction:
Improveresistance to Bi diffusionVSAvoidconnection member geometry
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent changes the geometric parameters of the connection member (flat bottom surface, decreasing diameter side surface) to control solder paste flow and prevent Bi diffusion. This geometric modification provides a passive structural solution to the diffusion problem

Inventive Principle:
Principle #35Parameter changes

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This design effectively prevents bi diffusion, reduces the risk of interface cracks, and enhances board level reliability by controlling solder paste flow and preventing brittleness, thereby improving the overall reliability of the semiconductor package.

Implementation Method 1

an oxide layer is formed on the side of the connection members

Methodology Applied
Scientific EffectDiffusion barrier: Diffusion Barrier

Implementation Method 2

a barrier layer is formed on the bottom surface and the side of the connection members

Methodology Applied
Scientific EffectDiffusion barrier: Diffusion Barrier

Data Source

PatentUS20240172371A1Semiconductor packages and method for fabricating the same
Publication Date: 2024.05.23 SAMSUNG ELECTRONICS CO LTD
  • US20240172371A1 patent drawing
  • US20240172371A1 patent drawing
  • US20240172371A1 patent drawing

AI summary

A semiconductor package includes a first structure, a second structure, a plurality of first connection members including SnBi; a plurality of second connection members including SAC (Sn, Ag and Cu). Each first connection member of the plurality of first connection members has a first surface and a second surface opposite each other, and the first surface of each first connection member of the plurality of first connection members is bonded to the first structure. A third surface of each second connection member of a plurality of second connection members is bonded to a corresponding second surface of a respective first connection member, and for each second connection member, a fourth surface of the second connection member that is opposite the third surface of the second connection member is bonded to the second structure. The third surface of each second connection member is flat, and a diameter of each second connection member decreases in a direction receding from the third surface of each second connection member.