Semiconductor Device Bias Data Generation Circuit
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Solution Overview
Problem
In AI technology, the increased arithmetic processing requirements lead to higher heat generation and power consumption, particularly due to the need for dedicated wiring for bias data supply and frequent readouts of weight data from memory cells, which can reduce arithmetic processing speed and increase circuit area and power consumption.
Innovation Solution
A semiconductor device with a novel structure comprising a storage circuit, an arithmetic circuit, and a driver circuit, where the arithmetic circuit includes a switching circuit and a product-sum operation circuit, and the storage circuit has separate regions for weight and bias data, allowing for efficient data processing and reduced power consumption by generating bias data within the arithmetic circuit, thus minimizing the need for additional wiring.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If dedicated wiring is provided for bias data supply in AI arithmetic processing circuits, then the arithmetic processing capability is improved, but the circuit area significantly increases
Solution Approach 1:
The patent merges the bias data storage function with the weight data storage function by using the same memory cell array for both types of data. The switching circuit selectively connects different memory regions (first region for weight data, second region for bias data) to the arithmetic circuit, eliminating the need for separate dedicated wiring for bias data supply and reducing overall circuit area while maintaining arithmetic processing capability
Solution Approach 2:
The memory cell array is designed to serve multiple functions: storing both weight data and bias data. The switching circuit enables the same memory structure to be universally used for different data types by selective connection, making the memory system multi-functional and reducing the need for specialized wiring for each data type
2Speed
If weight data is frequently read out from memory cell array through bit line for AI arithmetic processing, then the arithmetic processing speed is improved, but the charge and discharge energy of bit line increases leading to higher power consumption
Solution Approach 1:
The patent segments the memory cell array into multiple regions (first region for weight data, second region for bias data) and uses a switching circuit to selectively connect only the required region to the arithmetic circuit. This segmentation allows efficient access to specific data types without requiring the entire memory array to be activated, reducing unnecessary charge and discharge operations on bit lines and lowering power consumption while maintaining fast access speed
3Ease of manufacture
If the circuit structure is simplified to reduce area, then the manufacturing cost is reduced, but the arithmetic processing speed may be compromised
Solution Approach 1:
The patent introduces a dynamic switching circuit that can selectively connect different memory regions to the arithmetic circuit based on the data type required (weight data or bias data). This dynamic reconfiguration capability allows the simplified memory structure to maintain high arithmetic processing speed by providing fast access to the needed data region without requiring a more complex dedicated memory structure for each data type
Data Source
AI summary
A semiconductor device with a novel structure is provided. The semiconductor device includes a storage circuit, an arithmetic circuit, and a driver circuit. The arithmetic circuit includes a switching circuit and a product-sum operation circuit. The storage circuit includes a first storage region and a second storage region. The first storage region has a function of retaining first storage data. The second storage region has a function of retaining second storage data. The switching circuit has a function of outputting the first storage data or the second storage data to the product-sum operation circuit. The driver circuit has a function of outputting first input data or second input data to the product-sum operation circuit. The product-sum operation circuit has a function of retaining first output data obtained by arithmetic processing performed on the first input data and the first storage data selected by the switching circuit. The arithmetic circuit has a function of adding, to the first output data, second output data obtained by arithmetic processing performed on the second input data and the second storage data selected by the switching circuit.