Semiconductor Biasing Structure for Self-Isolating Buried Layer
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Solution Overview
Problem
Existing semiconductor device isolation schemes, such as junction isolation and SOI technologies, face challenges including larger chip sizes, high capacitance, thermal dissipation issues, and increased costs, while also being susceptible to parasitic currents that affect the stability and performance of functional devices.
Innovation Solution
A semiconductor device structure featuring a floating buried doped region within a trench isolation structure, where a biasing device is integrated to set the potential of the floating buried region and divert parasitic currents, thereby improving the performance and stability of functional devices, and reducing the effects of parasitic currents.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If junction isolation schemes are used, then electrical isolation between devices is achieved, but chip size increases and capacitance increases
Solution Approach 1:
The patent extracts the isolation function from traditional junction isolation by introducing a deep trench isolation structure that physically removes substrate material between devices. This trench extends through the entire substrate thickness, completely separating adjacent devices and eliminating parasitic currents while reducing the lateral space required for isolation compared to conventional junction isolation schemes.
Solution Approach 2:
The patent transitions from lateral isolation (in the plane of the substrate) to vertical isolation by creating deep trenches that extend through the substrate thickness. This dimensional change allows isolation to occur in the vertical dimension, enabling tighter lateral packing of devices while maintaining effective electrical isolation.
2Area of stationary object
If SOI technology is used, then chip size is reduced, but thermal dissipation deteriorates and manufacturing cost increases
Solution Approach 1:
The patent applies local quality by creating isolated regions of buried doped layers only where needed between specific devices, rather than using a global SOI structure. This allows selective thermal management in critical areas while maintaining good thermal contact with the substrate in other regions, achieving localized thermal dissipation improvement without sacrificing chip size benefits.
3Object-generated harmful factors
If deep trench isolation is used, then parasitic currents are reduced, but device complexity increases
Solution Approach 1:
The patent merges multiple functions into the deep trench isolation structure: it provides electrical isolation between devices, serves as a mechanical support structure, and acts as a pathway for biasing electrodes to reach buried doped layers. This consolidation reduces overall device complexity compared to using separate structures for each function.
Solution Approach 2:
The deep trench isolation structure serves multiple purposes simultaneously: isolating devices laterally, providing vertical access for biasing, supporting the overlying device structure, and reducing parasitic currents. This multi-functionality eliminates the need for additional dedicated structures, simplifying the overall device architecture.
Data Source
AI summary
A semiconductor device includes a floating buried doped region, a first doped region disposed between the floating buried doped region and a first major surface, and a semiconductor region disposed between the floating buried doped region and a second major surface. Trench isolation portions extend from the first major surface and terminate within the semiconductor region to define an active region. An insulated trench structure is laterally disposed between the trench isolation portions, terminates within the floating buried doped region, and defines a first portion and a second portion of the active region. A biasing semiconductor device is within the first portion, and a functional semiconductor device is within the second portion. The biasing semiconductor device is adapted to set a potential of the floating buried doped region and adapted to divert parasitic currents away from the functional semiconductor device.