Semiconductor Component Bilayer High-k Gate Dielectric
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Challenges in providing appropriate stress and/or gate resistance in metal gate FinFETs lead to degradation of device performance due to low stress and high gate resistance, affecting gate leakage and work function.
Innovation Solution
Implementing a gate last approach with a bilayer high-k gate dielectric structure, comprising a first high-k dielectric layer and a second high-k dielectric layer, along with a composite metal gate layer, to balance stress and resistance, and adjust threshold voltage for improved performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If a metal gate electrode is implemented in FinFET devices, then device performance is improved with decreased feature sizes, but gate leakage and work function control become problematic due to high gate resistance and low stress
Solution Approach 1:
The patent uses a composite metal gate electrode structure comprising multiple metal layers (e.g., tungsten, cobalt, copper, or nickel layers) with different properties. This composite structure allows optimization of gate resistance through conductive layers while providing appropriate stress control through layers with suitable mechanical properties, thereby resolving the contradiction between improved device performance and reliable gate leakage/work function control.
Solution Approach 2:
The patent adjusts physical and chemical parameters of the metal gate electrode by selecting different metal materials and controlling layer thicknesses. By changing the composition and structure parameters of the metal gate, the patent achieves optimal balance between gate resistance reduction and stress control, improving both device performance and reliability at scaled feature sizes.
2Stability of the object's composition
If the metal gate electrode is formed later in the process (gate last methodology), then stability of work function metal during processing is improved, but device complexity and fabrication steps increase
Solution Approach 1:
The patent forms the metal gate electrode structure later in the fabrication process after completing other critical device structures. This gate-last methodology allows preliminary formation of FinFET structures, isolation layers, and contact regions first, then introduces the metal gate electrode in subsequent steps, ensuring work function metal stability while managing fabrication complexity through sequential processing.
3Reliability
If low stress is applied to the gate, then device performance degradation occurs, but high stress increases manufacturing complexity
Solution Approach 1:
The patent incorporates stress control layers within the composite metal gate electrode structure. These layers are specifically designed to provide appropriate mechanical stress to the channel region, ensuring device performance reliability. The composite structure allows integration of stress control functionality without significantly increasing manufacturing complexity, as stress control is achieved through material selection and layer configuration rather than additional processing steps.
Data Source
AI summary
A semiconductor component, which includes a substrate, an interfacial layer disposed on the substrate, a first metal gate structure and a second metal gate structure disposed on the substrate. The first metal gate structure includes a first high-k dielectric layer disposed on the interfacial layer, and a first metal gate layer disposed on the first high-k dielectric layer. The second metal gate structure includes a second high-k dielectric layer disposed on the interfacial layer, a third high-k dielectric layer disposed on the second high-k dielectric layer, and a second metal gate layer disposed on the third high-k dielectric layer.