Semiconductor Integrated Circuit Logic BIST During Non-Access Periods
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Solution Overview
Problem
Existing methods for testing large-scale complex semiconductor integrated circuits, such as logic BIST, face challenges in ensuring reliability due to varying conditions between power-on and system operation, leading to incomplete testing and storage capacity issues.
Innovation Solution
A semiconductor integrated circuit design that performs logic BIST during non-access state periods, dividing tests into multiple periods and cumulatively compressing results for analysis, allowing for reliable testing under system operation conditions and reducing storage needs by comparing compressed values against pre-stored expected values.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If logic BIST is performed during system operation, then device reliability is improved, but testing can only be performed during non-access periods which limits test completeness
Solution Approach 1:
The patent divides the test into multiple segments executed during different non-access periods. The test control circuit performs logic BIST operations in discrete time slots when the tested block is not being accessed, breaking down the continuous test requirement into manageable segments that fit within available time windows.
Solution Approach 2:
The patent implements periodic testing by repeatedly executing logic BIST during each non-access period. The test control circuit periodically initiates test sequences during available time slots, ensuring continuous reliability verification without requiring dedicated continuous test time.
2Measurement precision
If test results are compressed and stored for analysis, then measurement precision is improved, but storage capacity requirements increase
Solution Approach 1:
The patent extracts only the essential test result data that is necessary for analysis while discarding redundant information. The compression logic identifies and retains only the critical failure indicators and test pattern outcomes, significantly reducing storage requirements while maintaining analysis precision.
Solution Approach 2:
The patent implements a selective data retention strategy where redundant test data is discarded during compression, but essential diagnostic information is recovered and preserved. The compression circuit eliminates duplicate test pattern results while maintaining the ability to reconstruct meaningful test outcomes for analysis.
Data Source
AI summary
According to one embodiment, a semiconductor integrated circuit comprises: a tested block including a test control circuit; and a control circuit configured to output a first signal. The test control circuit performs a test of at least a first test pattern of the test patterns for the scan chain in accordance with the first signal during a first non-access state period of the tested block, and performs a test of at least a second test pattern following the first test pattern of the test patterns for the scan chain in accordance with the first signal during a second non-access state period of the tested block, and the test of the first test pattern and the test of the second test pattern are performed discontinuously.