Semiconductor Bit Line Structure Etching Protection
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Solution Overview
Problem
In semiconductor manufacturing, the etching process for forming contact holes can erode bit line structures, leading to increased manufacturing complexity and cycle time, as well as difficulties in filling capacitor contact holes due to the height difference between bit line and inter-layer dielectric layers.
Innovation Solution
A semiconductor manufacturing method involving the formation of bit line structures with an inter-layer dielectric layer and a mask layer, where the upper surface of the bit line structures is lower than the inter-layer dielectric layer, allowing for selective etching that protects the bit line structures and optimizes the manufacturing process by preventing material erosion and reducing the need for backfilling.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If the upper surface of bit line structures is made level with the inter-layer dielectric layer, then the filling of capacitor contact holes is improved, but the etching process erodes the bit line structure material
Solution Approach 1:
The patent applies preliminary action by forming the bit line structures at a lower height than the inter-layer dielectric layer before the etching process. This pre-positioning prevents the bit line structures from being eroded during subsequent etching operations while maintaining the required height difference for proper capacitor contact hole filling. The bit line structures are formed first, then the inter-layer dielectric layer is formed on top, creating a stepped configuration that protects the bit lines during etching.
2Productivity
If the bit line structure height is reduced, then the manufacturing cycle is shortened, but the protection against etching erosion is compromised
Solution Approach 1:
The patent resolves this contradiction by establishing the lower bit line structure height as a preliminary configuration that inherently provides etching protection. By forming bit lines at a lower level before dielectric layer deposition, the structure achieves both reduced height for faster manufacturing and built-in protection against etching, eliminating the need for additional protective measures.
Solution Approach 2:
The inter-layer dielectric layer acts as an intermediary that protects the bit line structures during the etching process. The dielectric layer is formed on top of the bit lines and serves as a protective barrier, preventing direct exposure of the bit line material to etchants while allowing the bit lines to maintain their reduced height for manufacturing efficiency.
3Device complexity
If a single mask layer is used for etching, then the manufacturing process is simplified, but the protection of bit line structures during etching is insufficient
Solution Approach 1:
The patent applies segmentation by dividing the mask layer into multiple functional layers: a first mask layer that protects the bit line structures during etching, and a second mask layer that provides additional protection and defines the etching pattern. This segmented approach allows each mask layer to perform its specific function optimally, with the first mask layer specifically designed to protect the lower bit line structures while the second mask layer provides supplementary protection.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method reduces the height of bit line structures relative to the substrate, improves the filling of capacitor contact holes, and shortens the manufacturing cycle while maintaining the performance of bit line structures, thereby optimizing the manufacturing process and reducing costs.
Implementation Method 1
forming a mask layer having an etching window, the mask layer may include a first mask sublayer and a second mask sublayer, the first mask sublayer may be formed on the upper surface of the bit line structures... etching the inter-layer dielectric layer by using the mask layer as a mask
Implementation Method 2
etching the inter-layer dielectric layer by using the mask layer as a mask, to form a contact hole, the contact hole may expose the surface of the substrate
Data Source
AI summary
A semiconductor structure and a manufacturing method thereof are present. The method includes: forming a first mask layer having an etching window, wherein the first mask layer includes a first mask sublayer formed on the upper surface of bit line structures, and a second mask sublayer located on the upper surface of the first mask sublayer and the upper surface of an inter-layer dielectric layer, the first mask sublayer has the upper surface level with the upper surface of an inter-layer dielectric layer, and has a plurality of strip-shaped patterns extending in a first direction and spaced apart from each other, and the second mask sublayer has a plurality of strip-shaped patterns extending in a second direction and spaced apart from each other; and etching the inter-layer dielectric layer by using the first mask layer as a mask to form a contact hole exposing a surface of a substrate.