Semiconductor Memory Bit Line Negative Potential Read Circuit
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Solution Overview
Problem
Existing semiconductor memory circuits face challenges in reducing power consumption and maintaining stable read operations as the power source voltage is lowered, due to high power efficiency requirements for driving multiple voltage lines and limitations in gate voltages for PMOS transistors.
Innovation Solution
A semiconductor device configuration that includes a memory cell, a precharge circuit, a negative potential applying circuit, and a sense amplifier, where the bit lines are precharged to ground potential and a negative potential is applied to create a potential difference for data reading, with the absolute value of the negative potential being smaller than the difference between the bit line potentials, allowing for reduced power consumption and stable read operations at lower power source voltages.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If the power source voltage is lowered to reduce power consumption, then power consumption is reduced, but the threshold voltage of MOS transistor comes close to power source voltage making fast read difficult
Solution Approach 1:
The patent applies parameter changes by introducing a negative potential (e.g., -0.8V to -1.2V) on the bit line during read operations. This modifies the voltage parameters of the system to create a larger potential difference between bit lines, thereby enhancing the sense amplifier's ability to detect signal changes even at reduced power source voltages (e.g., 1.8V or lower). The negative potential adjustment compensates for the reduced threshold voltage margin and maintains fast read performance while achieving low power consumption.
2Reliability
If multiple voltage lines (word line, dummy word line, voltage line) are driven at high voltage to maintain operation, then read operation stability is maintained, but current efficiency of power source deteriorates
Solution Approach 1:
The patent extracts and eliminates the need for separate high-voltage driving of multiple voltage lines (word line, dummy word line, voltage line) by using a single negative potential applied to the bit line. This simplifies the voltage control architecture and reduces the total current drawn from the power source. The negative potential on the bit line serves multiple functions: creating the potential difference for reading, maintaining operation stability, and eliminating the need for separate high-voltage driving circuits, thereby significantly improving current efficiency.
3Use of energy by moving object
If gate voltage for PMOS transistor is reduced to lower power consumption, then power consumption is reduced, but operating rate of sense amplifier deteriorates
Solution Approach 1:
The patent changes the voltage parameters by applying a negative potential to the bit line, which creates a larger potential difference that enhances the sense amplifier's operating rate. This allows the sense amplifier to operate at high speed even when the power source voltage and gate voltage for PMOS transistors are reduced. The negative potential effectively compensates for the reduced voltage headroom, maintaining fast operation while achieving low power consumption.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution enables reduced power consumption and stable read operations in semiconductor devices with embedded DRAM, even at lower power source voltages, by optimizing the potential differences and reducing the influence of production tolerance on the read operation.
Implementation Method 1
a precharge circuit configured to be connected to the first bit line and a second bit line and precharge the first bit line and the second bit line to a ground potential
Implementation Method 2
a negative potential applying circuit configured to be connected to the first bit line and apply a negative potential to the first bit line
Implementation Method 3
a sense amplifier configured to be connected to the first bit line and the second bit line and read data based on a difference between a first potential of the first bit line and a second potential of the second bit line
Data Source
AI summary
A semiconductor device includes: a memory cell; a precharge circuit; a negative potential applying circuit; and a sense amplifier. The memory cell is connected to a first bit line and store data. The precharge circuit is connected to the first and second bit lines and precharges the first and second bit lines to a ground potential. The negative potential applying circuit is connected to the first bit line and applies a negative potential to the first bit line. The sense amplifier is connected to the first and second bit lines and read data based on a difference between a first potential of the first bit line and a second potential of the second bit line. An absolute value of the negative potential is smaller than the difference between the first potential and the second potential.