Semiconductor Integrated Circuit Bit Line Pair for Product-Sum Operations
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Solution Overview
Problem
The reduction in power supply voltage for semiconductor integrated circuits makes it difficult to accurately identify product-sum operation values from the potential levels of wiring, leading to potential errors in machine learning processes, especially in convolutional neural networks where numerous product-sum operations are required.
Innovation Solution
A semiconductor integrated circuit design featuring a bit line pair that discharges differently based on multiplication results, using two word lines to supply second data and a selection circuit to identify the correct bit line for discharge, ensuring accurate representation of product-sum operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If power supply voltage is reduced to improve power efficiency, then energy consumption decreases, but the ability to accurately identify product-sum operation values from wiring potential levels deteriorates
Solution Approach 1:
The patent divides the identification process into two segments: first, a selection circuit identifies which bit line discharged based on potential level; second, a read circuit identifies the discharge state. This segmentation allows accurate identification even at low voltage by separating the identification tasks into stages with different voltage requirements.
Solution Approach 2:
The patent introduces a selection circuit as an intermediary between the bit lines and the read circuit. This selection circuit uses a small amount of voltage to identify which bit line discharged, then directs the read circuit to read only that specific bit line. The intermediary selection circuit enables accurate identification without requiring high voltage across all bit lines simultaneously.
2Device complexity
If a single bit line is used to output product-sum operation results, then device complexity is reduced, but measurement precision of operation values deteriorates due to overlapping potential levels
Solution Approach 1:
The patent segments the output structure into multiple bit lines (first bit line and second bit line) where each bit line carries a portion of the product-sum operation results. The selection circuit then segments the identification process by selecting which bit line to read based on discharge patterns. This segmentation prevents potential level overlap confusion while maintaining manageable device complexity.
Solution Approach 2:
The patent transitions from a one-dimensional single bit line output to a two-dimensional structure with multiple bit lines and a selection dimension. The selection circuit adds a new dimension of control by selecting which bit line to activate and read, enabling precise identification of product-sum operation values without requiring a single complex high-voltage bit line.
Data Source
AI summary
A semiconductor integrated circuit has a plurality of memory cells arranged in a first direction and each storing first data, a plurality of first wirings provided to correspond to the plurality of memory cells arranged in the first direction and supplying second data to be multiplied by the first data, and a second wiring pair provided to correspond to the plurality of memory cells arranged in the first direction and that includes one second wiring which is discharged when multiplication data of the first data, stored in each of the plurality of memory cells, and the second data, supplied by the first wiring corresponding to the memory cell, is a first logic; and another second wiring which is discharged when the multiplication data is a second logic.