Semiconductor Device Bit Line Planarization
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Solution Overview
Problem
As the integration level of DRAM devices increases, non-uniformity in the surfaces of layers on a substrate leads to defects in pattern formation, affecting the operating characteristics of memory cells and causing cutting defects in bit line structures due to protrusions at the edge portions.
Innovation Solution
A semiconductor device is manufactured with a substrate having regions with differently sized trenches, where buried insulation layers are sequentially stacked and planarized to create a flat surface, allowing for uniform formation of structures and reducing protrusions, thereby minimizing defects in the bit line structure.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the integration level of DRAM devices is increased, then the density and capacity of the device are improved, but non-uniformity in the surfaces of layers occurs leading to defects in pattern formation
Solution Approach 1:
The substrate is divided into first and second regions with different trench configurations. The first region has a first trench while the second region has a second trench, allowing different areas to be optimized for different functions. This segmentation enables the high-density memory cell region to coexist with a flattened bit line region, resolving the conflict between integration density and surface uniformity.
Solution Approach 2:
Different regions of the substrate are given different local characteristics: the first region maintains trenches for high-density memory cells, while the second region has trenches filled with buried insulation layers to create a flattened surface. This local differentiation allows each region to optimize for its specific function - either density or surface uniformity - without compromising the other.
2Quantity of substance
If trenches are formed in the substrate for memory cell structures, then the storage capacity is improved, but protrusions occur at edge portions causing cutting defects in bit line structures
Solution Approach 1:
The problematic protrusions at the edge portions are extracted and removed by filling the second trench with buried insulation layer patterns. This extraction eliminates the source of cutting defects while preserving the memory cell structure in the first region, thereby maintaining storage capacity while improving reliability.
Solution Approach 2:
Buried insulation layers are introduced as intermediary structures between the substrate and the bit line structure. These insulation layers fill the second trench and provide a transitional, flattened surface that prevents direct contact between the protruding trench edges and the bit line, thereby eliminating cutting defects while allowing the underlying memory cell structure to remain intact.
3Manufacturing precision
If multiple buried insulation layer patterns are stacked in the second trench, then the flatness of the upper surface is improved, but the device structure becomes more complex
Solution Approach 1:
Instead of attempting to flatten the surface by modifying the horizontal geometry of the trench, the solution moves to the vertical dimension by stacking multiple buried insulation layers. This dimensional transition allows the trench to be filled in a way that creates a flattened upper surface, achieving the desired flatness while containing the complexity within a vertical stack rather than spreading it horizontally.
Data Source
AI summary
A semiconductor device includes a substrate including a first region having a first trench and a second region having a second trench. A first buried insulation layer pattern is disposed in the first trench. The second trench includes the first buried insulation layer pattern, a second buried insulation layer pattern, and a third buried insulation layer pattern sequentially stacked therein. A first buffer insulation layer is disposed on the substrate in the first and second regions and has a flat upper surface. A second buffer insulation layer is disposed on the first buffer insulation layer. A bit line structure is disposed on the first and second regions. A first portion of the bit line structure is disposed on the second buffer insulation layer and has a flat lower surface. A second portion of the bit line structure directly contacts a surface of the substrate in the first region.