Semiconductor Bit Line Trench Structure for Parasitic Capacitance Reduction
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Solution Overview
Problem
As electronic devices become smaller and lighter, semiconductor devices require higher integration with reduced design rules, leading to increased aspect ratios of conductive patterns, which poses challenges in reducing parasitic capacitance and maintaining reliability.
Innovation Solution
A semiconductor device design featuring a bit line with a reduced aspect ratio, achieved through a thin conductive pattern and a peripheral gate structure with a stacked configuration, where the bit line's upper surface is lower than the peripheral gate electrode's surface, reducing parasitic capacitance and improving manufacturing productivity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If design rules are reduced to increase integration density, then device integration is improved, but aspect ratio of conductive patterns increases
Solution Approach 1:
The patent transitions from a planar bit line structure to a three-dimensional structure where the bit line is positioned in a trench below the peripheral gate structure level. This vertical dimensionality change allows reduced aspect ratio of the bit line while maintaining high integration density through effective use of vertical space in the device architecture.
2Productivity
If aspect ratio of conductive patterns is increased due to reduced design rules, then integration density is improved, but parasitic capacitance increases
Solution Approach 1:
The patent extracts the bit line from the conventional planar configuration and relocates it to a separate trench structure below the peripheral gate level. This separation removes the bit line from the high-capacitance environment at the gate level, effectively reducing parasitic capacitance while maintaining integration density.
Solution Approach 2:
The patent employs a thin conductive pattern for the bit line in the trench structure, using a simplified single-layer conductive material rather than multi-layer structures. This reduces the capacitance-forming surface area while maintaining electrical functionality, effectively reducing parasitic capacitance.
3Ease of manufacture
If conventional planar bit line structure is used, then manufacturing is simple, but parasitic capacitance is high and reliability is reduced
Solution Approach 1:
The patent segments the bit line structure from the peripheral gate structure by positioning the bit line in a separate trench below the gate level. This segmentation reduces parasitic capacitance between bit lines and gates, improving reliability while the trench structure itself provides a straightforward manufacturing approach using standard etching and deposition techniques.
Data Source
AI summary
A semiconductor device includes a substrate including a cell active region and a peripheral active region, a direct contact arranged on a cell insulating pattern formed on the substrate and connected to the cell active region, a bit line structure including a thin conductive pattern, contacting a top surface of the direct contact and extending in one direction, and a peripheral gate structure in the peripheral active region. The peripheral gate structure include a stacked structure of a peripheral gate insulating pattern and a peripheral gate conductive pattern, the thin conductive pattern includes a first material and the peripheral gate conductive pattern include the first material, and a level of an upper surface of the thin conductive pattern is lower than a level of an upper surface of the peripheral gate conductive pattern.