Semi-buried Bit Line Structure for DRAM Stability
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Solution Overview
Problem
The structural instability of bit lines in dynamic random access memory (DRAM) devices leads to poor electrical performance and high manufacturing costs due to complex preparation processes, especially for devices with critical sizes less than 20 nanometers.
Innovation Solution
A method for forming a semiconductor structure that includes etching bit line trenches in both the memory and insulating areas of a substrate, followed by the deposition and etching of metal layers to create a semi-buried bit line structure and peripheral gate, simplifying the process and improving stability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If bit lines are prepared separately from peripheral gates in peripheral areas, then the preparation process becomes complex and costly, but the structural stability of bit lines is compromised
Solution Approach 1:
The patent merges the formation of bit lines and peripheral gates into a single integrated process. The bit line structure extends continuously from the memory area through the peripheral area, where it is patterned to form peripheral gates. This eliminates the need for separate preparation processes while maintaining structural stability through the continuous bit line structure.
Solution Approach 2:
The bit line structure serves multiple functions: it acts as a bit line in the memory area and as a peripheral gate in the peripheral area. This multi-functionality is achieved by extending the bit line structure into the peripheral area and patterning it to form gate structures, thereby eliminating the need for separate peripheral gate formation processes.
2Ease of manufacture
If bit lines are formed with complex separate preparation processes, then manufacturing cost increases, but electrical performance deteriorates due to structural instability
Solution Approach 1:
The patent combines the formation of bit lines and peripheral gates into a single process flow, reducing manufacturing steps and costs. The continuous bit line structure provides structural stability that ensures reliable electrical performance, while the integrated process reduces complexity and cost.
3Ease of manufacture
If bit lines are located on the surface of active areas, then the structure is simple to form, but the structural stability is poor leading to poor electrical performance
Solution Approach 1:
The patent transitions from surface-level bit line formation to a semi-buried structure by etching trenches into the substrate and filling them with conductive material. This dimensional change from surface to subsurface provides enhanced structural stability while maintaining manufacturing simplicity through the continuous formation process.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach stabilizes the bit line structure, simplifies the manufacturing process, reduces costs, and enhances the electrical performance of DRAM devices by allowing simultaneous formation of semi-buried bit lines and peripheral gates.
Implementation Method 1
The insulating layer and the memory area of the semiconductor substrate are etched to form a plurality of bit line trenches arranged at intervals along a first direction
Implementation Method 2
A second metal layer is formed on a surface of the bit line trench, the surface of the memory area and a surface of the first metal layer
Data Source
AI summary
A method for forming a semiconductor structure includes: providing a semiconductor substrate including a memory area and a peripheral area; forming an insulating layer on a surface of the memory area, and forming a first metal layer on a surface of the peripheral area; etching the insulating layer and the memory area of the semiconductor substrate to form a plurality of bit line trenches arranged at intervals along a first direction and etched insulating layer, in which part of the bit line trench is located in the memory area of the semiconductor substrate, and the other part of the bit line trench is located in the etched insulating layer; forming a second metal layer on surfaces of the bit line trench, the memory area and the first metal layer; and etching the first metal layer and the second metal layer to form a semi-buried bit line structure and peripheral gate.