Semiconductor Bit-Line Structure Integration for Reduced Resistance
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Solution Overview
Problem
The complexity and miniaturization of semiconductor devices pose challenges in creating smaller line widths and efficient data storage elements, particularly in the integration of bit-line structures and contact plugs, which can lead to increased fabrication costs and process failures.
Innovation Solution
The semiconductor memory device design includes a bit-line structure with a contact part and a line part integrated into a single unitary piece, formed of metallic material to reduce resistance, and uses intermediate dielectric patterns with capping and fence parts to facilitate the formation of contact plugs without additional fence structures, thereby simplifying the fabrication process and reducing the number of process steps.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If bit-line structures and contact plugs are separately formed with additional fence structures, then alignment precision can be improved, but device complexity and fabrication cost increase
Solution Approach 1:
The patent merges the bit-line structure and contact plug formation into a single integrated structure. The bit-line structure includes contact parts that directly extend to contact the second impurity regions, eliminating the need for separate fence structures. This integration reduces the number of fabrication steps while maintaining precise alignment through the continuous metallic material formation process.
Solution Approach 2:
The bit-line structure serves multiple functions simultaneously: it acts as both the bit-line conductor and the contact structure. The contact parts of the bit-line structure directly contact the second impurity regions, combining the functions of separate bit-line and contact plug structures into a single multi-functional element, thereby simplifying the overall device architecture.
2Reliability
If bit-line structures use metallic material, then electrical resistance is reduced, but fabrication process complexity increases
Solution Approach 1:
The patent combines the formation of metallic bit-line structures with the existing CMOS fabrication process. The metallic material is deposited and patterned in the same process sequence used for forming other conductive structures, merging multiple functions into a unified fabrication approach rather than adding separate complex metal processing steps.
3Ease of manufacture
If intermediate dielectric patterns include fence parts, then contact plug formation is facilitated, but device complexity increases
Solution Approach 1:
The patent extracts and removes the fence parts from the intermediate dielectric patterns, retaining only the capping parts that cover the word lines. The contact plugs are formed by directly removing sacrificial dielectric material in recess regions, eliminating the need for fence structures while simplifying the intermediate dielectric pattern design and reducing fabrication complexity.
Data Source
AI summary
A semiconductor memory device includes active sections that include first and second impurity regions and are defined by a device isolation layer. Word lines extend in a first direction on the active sections. Intermediate dielectric patterns cover top surfaces of the word lines. Bit-line structures extend on the word lines in a second direction intersecting the first direction. Contact plugs are disposed between the bit-line structures and are connected to the second impurity regions. Data storage elements are disposed on the contact plugs. The intermediate dielectric pattern includes a capping part that covers the top surfaces of the word lines and is buried in the substrate. Fence parts extend between the bit-line structures from the capping part.