Semiconductor Bitline Spacer Gap Formation
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Solution Overview
Problem
The high manufacturing cost of semiconductor structures due to the need for multiple photomasks and the resulting large parasitic capacitance between adjacent bitlines and contact structures, which affects electrical properties.
Innovation Solution
A manufacturing method that uses a first mask layer and a second mask layer with complementary patterns to reduce the number of photomasks required and creates a gap between spacer layers and bitlines, allowing for the formation of contact hole structures and improving electrical properties by reducing parasitic capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If multiple photomasks are used for different mask layers with different patterns, then the semiconductor structure can be manufactured with required functionality, but the manufacturing cost increases
Solution Approach 1:
The patent combines multiple photomask functions into a single photomask by superimposing different patterns (first pattern for active region, second pattern for contact holes, third pattern for bitlines) on the same mask layer. This merging approach eliminates the need for multiple separate photomasks, thereby reducing manufacturing cost while maintaining the ability to create diverse mask layer patterns through selective etching and spacer formation processes
2Manufacturing precision
If photomasks are used for manufacturing mask layers, then the required patterns can be formed, but the manufacturing cost increases due to photomask writing machine costs, software costs, and manual development costs
Solution Approach 1:
The patent merges multiple photomask requirements into a single photomask design that contains all necessary patterns (active region definition, contact hole positioning, bitline patterns) in different layers or regions. This single photomask approach eliminates repeated photomask writing machine usage, software licensing costs, and manual development expenses associated with multiple photomasks, while maintaining high manufacturing precision through the integrated pattern design
3Productivity
If adjacent conductive structures have shortened distance to achieve smaller semiconductor process, then the integration density increases, but parasitic capacitance problems occur between adjacent bitlines, between bitline and contact structure, and between adjacent contact structures
Solution Approach 1:
The patent introduces a dielectric layer as an intermediary substance between adjacent conductive structures (bitlines and contact holes). This dielectric layer acts as a mediator that reduces the electrical coupling between nearby conductors, thereby minimizing parasitic capacitance effects while allowing the conductive structures to remain closely spaced for high integration density. The dielectric material serves as a buffer that enables close packing without suffering from excessive capacitive coupling
Data Source
AI summary
An embodiment of the present application provides a manufacturing method of a semiconductor structure, including: providing a base; forming a first mask layer with a first mask pattern on the base, and etching the base with the first mask layer as a mask to form an active region; forming a plurality of discrete bitlines on the active region; sequentially stacking a first spacer layer and a second spacer layer on a side wall of the bitline; forming a sacrificial layer between the adjacent second spacer layers; forming a second mask layer with a second mask pattern on the sacrificial layer, the first mask pattern being complementary to the second mask pattern; etching the sacrificial layer with the second mask layer and the bitline as masks to form multiple contact hole structures; and etching the first spacer layer to form a gap between the second spacer layer and the bitline.