Semiconductor Device Blocking Pattern for Etchant Isolation
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Solution Overview
Problem
The challenge in manufacturing three-dimensional non-volatile memory devices lies in replacing nitride layers with conductive layers, which often damages peripheral layers and deteriorates the device's characteristics.
Innovation Solution
A semiconductor device with alternating conductive and insulating layers, including air gaps and blocking patterns, is designed to facilitate the replacement of sacrificial layers with conductive layers, preventing etchant damage and maintaining structural integrity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If nitride layers are replaced with conductive layers in the conventional process, then gate electrodes are formed, but peripheral layers are damaged and device characteristics deteriorate
Solution Approach 1:
The device is divided into a memory cell region and a peripheral region, with the blocking pattern creating a physical separation. This segmentation allows the peripheral region to be isolated from etchant damage that occurs during nitride layer replacement in the memory cell region, enabling gate electrode formation without compromising peripheral layer integrity
Solution Approach 2:
The blocking pattern acts as an intermediary structure between the memory cell region and peripheral region. It serves as a protective barrier that prevents etchant from reaching peripheral layers during the nitride layer replacement process, while still allowing the overall manufacturing process to proceed
2Device complexity
If nitride layers are replaced with conductive layers, then stacked gate electrodes are formed, but the replacement process is difficult to perform
Solution Approach 1:
The blocking pattern is strategically placed only in the peripheral region, creating different local conditions: the memory cell region allows nitride layer replacement to form conductive layers, while the peripheral region maintains the blocking pattern for protection. This local differentiation enables the complex stacked gate structure to be formed without making the overall replacement process excessively difficult
3Quantity of substance
If three-dimensional structure is implemented to increase integration, then memory cell capacity increases, but manufacturing complexity increases
Solution Approach 1:
By segmenting the device into memory cell and peripheral regions with distinct structures, the patent enables three-dimensional stacking in the memory cell region to increase integration capacity, while the simpler peripheral region maintains easier manufacturability. The blocking pattern facilitates this segmented approach
Data Source
AI summary
A semiconductor device including a first stacked structure including first conductive layers and first insulating layers stacked alternately with each other, first semiconductor patterns arranged in a first direction, wherein each of the first semiconductor patterns passes through the first stacked structure in a stacking direction, a second stacked structure including second conductive layers and second insulating layers stacked alternately with each other, second semiconductor patterns arranged in the first direction and adjacent to the first semiconductor patterns in a second direction crossing the first direction, wherein each of the second semiconductor patterns passes through the second stacked structure in the stacking direction, a third stacked structure including air gaps and third insulating layers stacked alternately with each other and located between the first and second structures, and at least one blocking pattern passing through the third stacked structure in the stacking direction and contacting the first and second structures.