Semiconductor Interconnection Blocking Patterns for Parasitic Capacitance Reduction
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Solution Overview
Problem
As semiconductor devices become highly integrated, the reduction in pattern pitches leads to increased parasitic capacitance, which in turn increases RC delay, necessitating effective methods to reduce capacitance while maintaining design flexibility.
Innovation Solution
The semiconductor device incorporates a design with first and second interconnection lines and blocking patterns of varying widths, along with air gaps in the insulating layer, to reduce parasitic capacitance, where the air gaps are strategically placed between the interconnection lines and blocking patterns, and the blocking patterns are formed using materials with etch selectivity to the insulating layer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If pattern pitches are reduced to achieve high integration, then device integration density is improved, but parasitic capacitance increases
Solution Approach 1:
The patent extracts the harmful capacitive coupling effect by introducing air gaps that physically separate interconnection lines, removing the parasitic capacitance source while maintaining the dense interconnection layout
Solution Approach 2:
The patent uses air gaps (porous structure) between interconnection lines to reduce parasitic capacitance, applying the principle of using void spaces to decrease electrical coupling while preserving spatial efficiency
2Reliability
If air gap formation is expanded to reduce parasitic capacitance, then RC delay is decreased, but mask margin limitations arise
Solution Approach 1:
The patent introduces blocking patterns as intermediary structures that facilitate air gap formation without requiring direct mask definition of the air gaps themselves, thereby avoiding mask margin limitations while achieving the desired capacitance reduction
Solution Approach 2:
The patent performs preliminary formation of blocking patterns that define the boundaries where air gaps will subsequently be created, preparing the structure in advance to enable air gap formation without direct mask involvement
3Adaptability or versatility
If blocking patterns of varying widths are used, then design flexibility is improved, but device complexity increases
Solution Approach 1:
The patent applies local quality by varying blocking pattern widths at different locations according to specific design requirements, allowing optimized capacitance reduction and signal integrity at each interconnection segment while maintaining overall patternability through systematic design rules
Data Source
AI summary
A semiconductor device including a first interconnection line having a first end and extending in a first direction; a first blocking pattern at the first end of the first interconnection line and adjacent to the first interconnection line in the first direction; a second interconnection line spaced apart from the first interconnection line in a second direction crossing the first direction and extending in the first direction, the second interconnection line having a second end; and a second blocking pattern at the second end of the second interconnection line and adjacent to the second interconnection line in the first direction, wherein a width of the first blocking pattern in the first direction is different from a width of the second blocking pattern in the first direction.