Semiconductor Body Contact Through Gate for Floating Effect
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Solution Overview
Problem
Semiconductor devices with stacked transistors face issues due to the floating body effect, which causes kink and parasitic bipolar effects, leading to undesired leakage currents and operational deterioration.
Innovation Solution
A semiconductor device structure with a body contact through a gate is implemented, where a body pattern is formed with a portion overlapping the gate electrode, and a body contact plug connects the upper and lower gate electrodes, ensuring electrical connection and reducing the floating body effect.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If transistors are stacked to achieve high integration density, then integration density is improved, but floating body effect occurs causing kink and parasitic bipolar effects
Solution Approach 1:
The patent implements a nested structure where a first transistor is formed on the semiconductor substrate and a second transistor is formed on the first transistor. The body layer of the second transistor is positioned over the channel region of the first transistor, creating a vertically stacked configuration that achieves high integration density while maintaining electrical isolation through insulating layers.
Solution Approach 2:
The patent introduces an insulating layer between the first and second transistors, and a cap oxide layer between the bulk transistor and the thin film transistor. These intermediary insulating layers provide electrical isolation that prevents the floating body effect while allowing the stacked configuration to achieve high integration density.
2Device complexity
If channel region is electrically isolated by insulating layers, then transistor stacking is enabled, but voltage variation occurs in the channel region
Solution Approach 1:
The patent addresses voltage variation in the isolated channel region by establishing equipotential connections. The body layer is divided into source/drain regions and a channel region, with the gate electrode positioned over the channel region. The insulating layers and cap oxide are configured to maintain electrical isolation while allowing controlled voltage distribution to prevent unwanted voltage variations in the channel region.
Data Source
AI summary
According to an embodiment of the invention, a lower transistor is formed on a semiconductor substrate, and an upper thin film transistor is formed on the lower transistor. A body contact plug is formed to penetrate an upper gate electrode of the upper thin film transistor and a body pattern, and to electrically connect with a lower gate electrode of the lower transistor. The body contact plug uses a contact hole to apply an electrical signal to the upper gate electrode of the upper thin film transistor, so additional volume is not necessary. Since the upper gate electrode is electrically connected to the body pattern through the body contact plug, the floating body effect of the upper thin film transistor can be improved. Therefore, a semiconductor device is provided with the high performance required to realize a highly-integrated semiconductor device.