Semiconductor Bond Width Variation for Strain Reduction
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Solution Overview
Problem
The packaging of integrated circuit (IC) chips faces challenges due to strain caused by differing coefficients of thermal expansion (CTE) between materials in the package assembly, leading to costly yield reduction and reliability issues, particularly with flip chip technology where solder balls experience cracking during thermal cycling.
Innovation Solution
The solution involves varying the dimensions of the interface or bond between the semiconductor die and the packaging substrate by adjusting the ratio of bond widths in different regions, using conductive materials such as solder balls, micro bumps, copper pillars, or gold studs, to counteract strain, thereby balancing conductive material and dielectric strain.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If uniform bond widths are used across the semiconductor die, then manufacturing is simplified, but strain from CTE differences causes solder ball cracking and reliability issues
Solution Approach 1:
The patent applies local quality by varying the bond width of conductive pads across different regions of the semiconductor die. Specifically, conductive pads in outer regions have different widths compared to those in inner regions, creating non-uniform strain distribution that compensates for CTE differences between materials. This local variation in geometric properties resolves the contradiction by maintaining solder ball integrity through region-specific strain management while remaining compatible with standard bonding processes.
2Reliability
If the bond interface dimensions are varied to counteract strain, then solder ball cracking is reduced, but manufacturing complexity increases
Solution Approach 1:
The patent employs asymmetry by intentionally creating non-uniform bond widths across the die surface. The conductive pads are designed with different dimensions in different regions, breaking the symmetry of uniform bonding. This asymmetric design strategically places wider or narrower pads in specific locations to counteract the non-uniform strain fields generated by CTE mismatches, thereby reducing solder ball cracking while managing the increased manufacturing complexity through a systematic rather than arbitrary variation pattern.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces conductive material strain and maintains acceptable dielectric strain, enhancing the reliability and performance of the packaged semiconductor devices by specifying a ratio range of 1.0 to 1.3 for the bond widths, which minimizes fatigue and cracking, leading to improved device performance.
Implementation Method 1
Ball cracking is typically generated by strain caused by different coefficients of thermal expansion (CTE) between materials in the package assembly
Data Source
AI summary
A method of forming a device includes forming conductive pads on a semiconductor die. The conductive pads include a first conductive pad having a first width on a first region of the semiconductor die; and a second conductive pad having a second width on a second region of the semiconductor die. The method includes forming bonding pads on a substrate. The bonding pads include a third bonding pad having a third width on a third region of the substrate; and a fourth bonding pad having a fourth width on a fourth region of the substrate. The method further includes forming a conductive material coupled between the first conductive pad and the third bonding pad, and between the second conductive pad and the fourth bonding pad. A ratio A of the first width to the third width is different from a ratio B of the second width to the fourth width.