Semiconductor Device Bonded Metal Layer Current Distribution
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Solution Overview
Problem
Chip scale semiconductor packages face issues with non-uniform current density and current crowding due to limited conductivity, leading to reduced maximum allowable current and potential device failure from parasitic current paths and localized heating, especially in transient voltage suppression devices.
Innovation Solution
A semiconductor device structure is created by bonding a first semiconductor substrate with a metal layer to a second semiconductor substrate having active device regions and a metal layer, forming a buried metal layer for uniform current distribution and reducing on-resistance, while also incorporating trenches filled with insulating material to prevent parasitic current flow.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If contacts are arranged on one surface of the package (CSP configuration), then the package is direct surface mountable and compact, but current density becomes non-uniform and current crowding occurs at contact edges
Solution Approach 1:
The patent transitions from a planar contact arrangement to a three-dimensional structure by bonding a carrier substrate to the semiconductor substrate. This creates vertical current paths through the bonded interface, allowing current to flow from top contacts through the semiconductor layer to bottom contacts on the carrier substrate, thereby eliminating current crowding at single-surface contact edges while maintaining compact CSP dimensions.
Solution Approach 2:
The patent introduces a carrier substrate with metal layers as an intermediary element between the semiconductor substrate and the external environment. This carrier substrate acts as a mediator that distributes current uniformly across its surface area and provides additional contact surfaces, thereby resolving the current density non-uniformity problem while enabling direct surface mounting.
2Device complexity
If current flows laterally through the substrate to reach contacts on the same side, then the device structure is simplified, but on-resistance increases and heat dissipation decreases
Solution Approach 1:
The patent adds a vertical dimension to current flow by bonding the carrier substrate to the semiconductor substrate. Current can now flow vertically from top contacts through the semiconductor layer and bonded interface to bottom contacts on the carrier substrate, creating shorter and more direct current paths that reduce on-resistance while improving heat dissipation through the vertical thermal path.
3Ease of manufacture
If contacts are placed on the same surface, then manufacturing is simplified, but parasitic current paths occur between device structures
Solution Approach 1:
The patent segments the current paths by creating distinct top and bottom contact surfaces on the carrier substrate. This segmentation separates different device structures' current paths, preventing parasitic current flow between adjacent devices while maintaining simplified manufacturing through the bonded carrier substrate structure.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution achieves uniform current density across the device, reduces on-resistance by 180-990 mOhm, and enhances heat dissipation, improving the robustness and performance of semiconductor devices, particularly in transient voltage suppression applications.
Implementation Method 1
bonding the first metal layer of the first semiconductor substrate to the second metal layer of the second semiconductor substrate
Implementation Method 2
forming one or more trench regions extending from the first major surface to the opposing second major surface of the second semiconductor substrate. The method may further comprise filling the trench regions with an insulating material.
Implementation Method 3
enhances heat dissipation, improving the robustness and performance of semiconductor devices
Data Source
AI summary
A semiconductor device structure and method of manufacturing a semiconductor device is provided. The method includes providing a first semiconductor substrate having a first major surface and an opposing second major surface, the first major surface having a first metal layer formed thereon; providing a second semiconductor substrate having a first major surface and an opposing second major surface, with the second semiconductor substrate including a plurality of active device regions formed therein and a second metal layer formed on the first major surface connecting each of the plurality of active device regions; bonding the first metal layer of the first semiconductor substrate to the second metal layer of the second semiconductor substrate; and forming device contacts on the second major surface of the second semiconductor substrate for electrical connection to each of the plurality of active device regions.