Semiconductor Package Bonding with Air-Gap Recesses for Delamination Control

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Solution Overview

Problem

Existing semiconductor packages face challenges in integrating multiple components while maintaining reliability and preventing interfacial delamination and void formation during bonding processes.

Innovation Solution

A method involving the formation of air gaps between recesses in the insulating layers of semiconductor chips, combined with thermal compression bonding, to enhance the bonding quality and reliability of semiconductor packages.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If direct bonding technology is used to join semiconductor chips without adhesive film or connecting bumps, then integration density is improved, but interfacial delamination and void formation occur during bonding

Engineering Contradiction:
Improveintegration densityVSAvoidbonding reliability
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The patent introduces an air gap as an intermediary space between the bonding interfaces of two semiconductor chips. This air gap acts as a mediator that allows for controlled gas entrapment during the bonding process, preventing direct contact between potentially contaminated or misaligned surfaces, thereby reducing delamination and void formation while maintaining the direct bonding approach for high integration density

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The patent modifies the bonding interface parameters by creating recesses in the insulating layers that define controlled air gaps. By changing the physical parameters of the bonding interface (introducing void spaces at specific locations), the bonding process becomes more reliable as gas can be trapped in these predefined regions rather than forming random voids, thus improving bonding reliability without sacrificing integration density

Inventive Principle:
Principle #35Parameter changes

2Reliability

If recesses are formed in insulating layers to create air gaps, then bonding quality is improved by preventing delamination, but manufacturing complexity increases

Engineering Contradiction:
Improvebonding qualityVSAvoidmanufacturing complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent applies preliminary action by forming recesses in the insulating layers before the bonding process. These recesses are pre-configured to trap gas during bonding, preventing delamination. By preparing the structure in advance with the air gap already defined, the actual bonding process becomes simpler and more reliable, as the gas trapping function is built into the structure rather than requiring complex real-time control during bonding

Inventive Principle:
Principle #10Preliminary action

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The method improves the joining quality and reliability of semiconductor packages by trapping gas and preventing interfacial delamination, ensuring stable electrical connections and enhanced performance.

Implementation Method 1

bonding the rear insulating layer and the front insulating layer to each other and bonding the plurality of rear pads and the plurality of front pads to each other by performing a thermal compression process

Methodology Applied
Scientific EffectThermal compression:

Implementation Method 2

forming an air gap between the first recesses and the second recesses in a vertical direction perpendicular to the first lateral direction

Methodology Applied
Scientific EffectGas trapping:

Data Source

PatentUS20260011666A1Method of manufacturing semiconductor package including thermal compression process
Publication Date: 2026.01.08 SAMSUNG ELECTRONICS CO LTD
  • US20260011666A1 patent drawing
  • US20260011666A1 patent drawing
  • US20260011666A1 patent drawing

AI summary

A method of manufacturing a semiconductor package may include: preparing a semiconductor wafer including rear pads and a rear insulating layer surrounding the rear pads, the rear insulating layer including first recesses spaced apart from the rear pads in a first lateral direction; preparing second semiconductor chips including front pads and a front insulating layer surrounding the front pads, the front insulating layer including second recesses spaced apart from the front pads in the first lateral direction; forming an air gap between the first recesses and the second recesses in a vertical direction by disposing the second semiconductor chips on the semiconductor wafer, the rear pads contacting the front pads; and bonding the rear insulating layer and the front insulating layer to each other and bonding the rear pads and the front pads to each other by performing a thermal compression process.