Semiconductor Storage Device Bonding Detection via Chain Wiring

Resolve Bottlenecks,
Find Innovative SolutionsGenerate Solutions

Solution Overview

Problem

Existing semiconductor storage devices face challenges in ensuring reliable bonding and detecting misalignment between peripheral circuit chips and memory array chips, leading to potential defects and reduced operational reliability.

Innovation Solution

The implementation of a chain wiring and adjacent wirings in the end region of the semiconductor storage device, which allows for the detection of bonding failures and misalignment by measuring electrical resistance between conductive pads, facilitating the identification of peeling and misalignment issues.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If bonding is performed between peripheral circuit chips and memory array chips, then device functionality is achieved, but bonding failures and misalignment occur reducing reliability

Engineering Contradiction:

Improvebonding reliabilityVSAvoiddetection structure complexity

Core Design Contradiction:

ReliabilityVSDevice complexity

Solution Approach 1:

The patent implements detection wirings and detection pads before the actual bonding process. These detection structures are pre-configured on both the peripheral circuit chip and memory array chip, allowing misalignment and bonding failures to be detected immediately after bonding without requiring additional testing steps. This preliminary arrangement of detection elements enables proactive quality control.

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

The patent introduces detection wirings as intermediary elements that connect detection pads on different chips. These detection wirings serve as mediators to transmit electrical signals for measuring resistance values, enabling indirect detection of bonding quality and alignment accuracy without directly interfering with the functional circuitry of the devices being bonded.

Inventive Principle:

Principle #24Intermediary (Mediator)

2Reliability

If detection wirings and pads are added to detect bonding failures, then reliability is improved, but manufacturing complexity increases

Engineering Contradiction:

Improvebonding failure detection capabilityVSAvoidmanufacturing process simplicity

Core Design Contradiction:

ReliabilityVSEase of manufacture

Solution Approach 1:

The patent merges the detection function with the existing bonding structure by integrating detection pads and wirings into the chip design. Rather than adding separate external testing equipment or post-bonding inspection processes, the detection capability is combined with the bonding interface itself, allowing quality verification to occur as part of the manufacturing flow without requiring distinct additional steps.

Inventive Principle:

Principle #5Merging (Combining)

3Productivity

If misalignment between chips is not detected, then bonding speed is maintained, but defective devices are produced reducing productivity

Engineering Contradiction:

Improvedefective device reductionVSAvoidmisalignment detection difficulty

Core Design Contradiction:

ProductivityVSDifficulty of detecting and measuring

Solution Approach 1:

The patent replaces complex mechanical alignment verification methods with electrical resistance measurement. Instead of using optical microscopes, mechanical gauges, or other physical measurement tools to detect misalignment, the system uses electrical resistance values measured through detection pads and wirings to infer alignment status. This substitution simplifies the detection mechanism while improving measurement capability.

Inventive Principle:

Principle #28Mechanics substitution (Replace mechanical system)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach enables the easy detection of bonding failures and misalignment, reducing the number of defective devices and improving the operational reliability of semiconductor storage devices by facilitating analysis and productivity.

Implementation Method 1

measuring electrical resistance between conductive pads, facilitates the identification of peeling and misalignment issues

Methodology Applied

Scientific EffectElectrical Resistance: Electrical Resistance

Data Source

PatentUS11482514B2Semiconductor storage device including first pads on a first chip that are bonded to second pads on a second chip

Publication Date: 2022.10.25 KIOXIA CORP

AI summary

A semiconductor storage device includes first and second chips. The first chip includes memory cells provided on a first substrate in a memory cell region, a plurality of first pads provided on a first surface of the first substrate and disposed in an edge region of the first chip that surrounds the memory cell region, and a first conductive layer provided on the first substrate and electrically connected to the first pads. The second chip includes a first circuit provided on a second substrate in a circuit region, a plurality of second pads provided on the second substrate and disposed in an edge region of the second chip that surrounds the circuit region, and a second conductive layer provided on the second substrate and electrically connected to the second pads. The first pads of the first chip and the second pads of the second chip are bonded facing each other.