Semiconductor Hybrid Bonding Structure for Pad Alignment and Crack Relief
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Solution Overview
Problem
The hybrid bonding process in semiconductor packaging is hindered by surface topography deviations and process technology issues, leading to misalignment of bonding pads and potential cracks due to contact with dielectric layers.
Innovation Solution
The use of bonding pads with a rounded side shape and dielectric layers with chamfered edge portions around the bonding pads creates a space to prevent contact between the dielectric layers and bonding pads, thereby improving alignment and reducing the risk of cracks during the bonding process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If hybrid bonding is performed with standard flat bonding surfaces, then bonding process simplicity is maintained, but misalignment of bonding pads occurs due to surface topography deviation
Solution Approach 1:
The patent applies preliminary action by forming oblique edge portions on the dielectric layer before the bonding process. This pre-formed geometric feature creates a built-in alignment mechanism that compensates for surface topography deviations during bonding, ensuring precise alignment of bonding pads without requiring complex real-time adjustment processes.
Solution Approach 2:
The patent introduces asymmetry by forming oblique edge portions on the dielectric layer instead of using symmetric vertical edges. This asymmetric geometric feature creates a directional guide that naturally aligns bonding pads during the bonding process, transforming the alignment problem from a precision control challenge into a geometric constraint solution.
2Productivity
If bonding pads are positioned close to dielectric layer edges, then bonding density is increased, but cracks occur due to contact between bonding pads and dielectric layer
Solution Approach 1:
The patent applies beforehand cushioning by forming oblique edge portions on the dielectric layer that create a gradual transition zone between the dielectric layer and bonding pads. This geometric cushioning prevents sudden contact and stress concentration at sharp corners, eliminating the root cause of cracks while allowing bonding pads to be positioned close to the dielectric layer edges for high bonding density.
3Ease of manufacture
If edge of dielectric layer contacts bonding pad during bonding, then manufacturing steps are reduced, but edge of dielectric layer breaks due to contact impact
Solution Approach 1:
The patent applies spheroidality by forming oblique edge portions on the dielectric layer that create curved, rounded transitions instead of sharp vertical edges. This geometric modification distributes contact stress during bonding along the inclined surface rather than concentrating it at a single point, preventing edge breakage while maintaining manufacturing simplicity.
Data Source
AI summary
A semiconductor package according to an embodiment includes a first semiconductor die including a back side bonding structure; and a second semiconductor die including a front side bonding structure bonded to the back side bonding structure, wherein the back side bonding structure includes a first dielectric layer; and first bonding pads passing through the first dielectric layer, the front side bonding structure includes a second dielectric layer bonded to the first dielectric layer; and second bonding pads with each second bonding pad bonded to a respective first bonding pad and passing through the second dielectric layer, and the first dielectric layer includes oblique edge portions around the first bonding pads at the surface facing the second dielectric layer.