Semiconductor Bonding Structure Layout for CTE Stress Relief
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Solution Overview
Problem
The semiconductor industry faces challenges in manufacturing new packaging technologies for semiconductor devices due to stress exerted on layers caused by coefficient of thermal expansion (CTE) mismatch between multi-die structures and substrates, which affects the electrical and mechanical performance of bonding structures.
Innovation Solution
The formation of elongated connectors aligned with the center of multi-die structures or substrates, along with seal ring structures, reduces stress and improves bonding by maximizing the bonding area and using underfill materials to protect the bonding structures.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If new packaging technologies are developed for semiconductor devices, then integration density of electronic components is improved, but stress on layers due to CTE mismatch between multi-die structures and substrates worsens
Solution Approach 1:
An underfill material is introduced as an intermediary substance between the multi-die structure and the substrate. This underfill material has a coefficient of thermal expansion that matches the multi-die structure, serving as a thermal expansion mediator that reduces stress on dielectric layers during temperature changes while enabling high integration density through advanced packaging configurations.
2Reliability
If bonding structures are used to attach multi-die structures to substrates, then electrical and mechanical connection is achieved, but stress concentration and potential delamination or cracking worsen
Solution Approach 1:
The coefficient of thermal expansion parameter of the underfill material is specifically matched to that of the multi-die structure. This parameter change in the underfill material reduces thermal stress concentration around bonding structures during temperature cycling, preventing delamination and cracking while maintaining reliable electrical and mechanical connections.
3Area of stationary object
If smaller packages are used to accommodate reduced minimum feature size, then area and height of packages are reduced, but stress management and bonding reliability worsen
Solution Approach 1:
The underfill material provides localized stress relief specifically at the bonding interfaces between multi-die structures and substrates. By applying this stress-relief mechanism locally at critical bonding regions rather than uniformly throughout the package, reliable bonding is maintained in compact packages with reduced area and height.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively reduces stress on dielectric layers and improves the electrical and mechanical performance of bonding structures, preventing defects like delamination and cracking, and enhances the integration density of electronic components.
Implementation Method 1
stress exerted on layers caused by coefficient of thermal expansion (CTE) mismatch between multi-die structures and substrates
Data Source
AI summary
A semiconductor device and a method of forming the same are provided. The semiconductor device includes a die structure including a plurality of die regions and a plurality of first seal rings. Each of the plurality of first seal rings surrounds a corresponding die region of the plurality of die regions. The semiconductor device further includes a second seal ring surrounding the plurality of first seal rings and a plurality of connectors bonded to the die structure. Each of the plurality of connectors has an elongated plan-view shape. A long axis of the elongated plan-view shape of each of the plurality of connectors is oriented toward a center of the die structure.