Semiconductor Bonding Layout With Organic Buffer Against Passivation Cracks
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Solution Overview
Problem
The formation of cracks in the passivation layer during thermal processes for bonding conductive members to semiconductor elements can lead to short circuits between interconnects with different potentials, which is not effectively addressed by existing technologies.
Innovation Solution
A semiconductor device design where a conductive bonding material is separated from the passivation layer by an organic film layer thicker than the passivation layer itself, ensuring that the conductive member is not in direct contact with the passivation layer, thereby reducing the likelihood of crack formation and short circuits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the conductive bonding material is placed in direct contact with the passivation layer during thermal bonding processes, then electrical connection between the conductive member and connection pads is achieved, but cracks form in the passivation layer causing short circuits between interconnects with different potentials
Solution Approach 1:
The patent introduces an organic film layer as an intermediary between the conductive bonding material and the passivation layer. This organic film serves as a buffer that absorbs thermal stress during bonding processes, preventing direct contact between the conductive bonding material and the passivation layer, thereby avoiding crack formation while still enabling electrical connection through the organic film's conductive properties
Solution Approach 2:
The patent employs a composite structure consisting of multiple layers with different material properties: the organic film layer combines insulating properties to protect the passivation layer with conductive properties to enable electrical connection. This composite approach allows the system to simultaneously achieve electrical connectivity and mechanical protection against thermal stress-induced cracking
2Device complexity
If the passivation layer is made thinner to reduce device complexity, then manufacturing process is simplified, but the passivation layer becomes more susceptible to cracking during thermal processes
Solution Approach 1:
The patent applies beforehand cushioning by placing the organic film layer between the conductive bonding material and the passivation layer before thermal bonding occurs. This organic film acts as a pre-positioned buffer that absorbs and distributes thermal stress, protecting the passivation layer from cracking even when the passivation layer is made thinner to reduce device complexity
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design effectively limits crack formation in the passivation layer, preventing short circuits between the gate interconnect and connection pads, while maintaining a cost-effective and compact manufacturing process.
Implementation Method 1
The passivation layer formed on the gate interconnect is separated from the conductive bonding material by the organic film layer that is greater in thickness than the passivation layer
Implementation Method 2
A conductive bonding material such as solder may be disposed between the upper surface of the semiconductor element and the conductive member and then undergo a thermal process (e.g., reflowing of solder) to ensure the electrical connection
Data Source
AI summary
A semiconductor device includes a semiconductor element including a transistor, a gate interconnect electrically connected to a gate electrode and extending in a first direction, two connection pads electrically connected to a source or drain electrode and separated in a second direction orthogonal to the first direction in plan view, a passivation layer formed on the gate interconnect, and an organic film layer formed on the passivation layer, a conductive bonding material disposed on the semiconductor element and at least partially overlapping the gate interconnect and the connection pads in plan view, and a conductive member disposed on the conductive bonding material. The connection pads are electrically connected to the conductive member via the conductive bonding material. The gate interconnect is disposed between the connection pads in plan view. The passivation layer is separated from the conductive bonding material by the organic film layer being thicker than the passivation layer.