Semiconductor Device Bonding Pad Configuration
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Solution Overview
Problem
Existing semiconductor devices face challenges in downsizing due to the need for large bonding pads for wire bonding, which can lead to degradation of device characteristics and sensitivity to electric potential changes, especially when using compound semiconductor devices for high-voltage and high-current applications.
Innovation Solution
A semiconductor device configuration featuring an active region covered by a first insulating layer, a floating conductor, a second insulating layer, and a bonding pad formed on the second insulating layer, with interconnection vias connecting the active region to the bonding pad, allowing for reduced space requirements and minimizing the impact of electric potential changes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If bonding pads are arranged in a region surrounding the active region for wire bonding, then reliable electrical connection is achieved, but the overall device size increases
Solution Approach 1:
The patent moves bonding pads from the traditional planar arrangement surrounding the active region to a three-dimensional configuration where pads are arranged on different levels (upper and lower surfaces) and at different heights using elevated structures. This vertical dimensionality change allows bonding pads to be positioned closer to the active region while maintaining adequate spacing, thereby reducing the overall device footprint without compromising electrical connection reliability.
2Area of stationary object
If bonding pads are arranged on the active region to reduce area, then device size is downsized, but electrical characteristics degrade due to electric potential changes
Solution Approach 1:
The patent introduces intermediary structures including insulating layers and elevated support structures between the bonding pads and the active region. These intermediaries electrically isolate the bonding pads from direct interaction with the active region, preventing electric potential changes at the bonding pads from directly affecting the active region's electrical characteristics, thus maintaining stability while enabling compact arrangement.
Solution Approach 2:
The patent segments the bonding pad structure into multiple independent elements distributed across different locations and heights rather than using large continuous pads. This segmentation allows the bonding pads to be arranged in a compact configuration near the active region while reducing the capacitive coupling and electric field interference that would otherwise degrade electrical characteristics.
3Manufacturing precision
If dry etching is used to form source electrode by etching insulating layer, then precise electrode formation is achieved, but manufacturing complexity increases due to process control difficulty
Solution Approach 1:
The patent extracts the insulating layer formation step from the critical path of source electrode formation. By pre-forming the insulating layer as a separate, non-critical layer before electrode patterning, the subsequent electrode formation processes can proceed with standard techniques without the need for precise dry etching control, thereby maintaining manufacturing precision while simplifying process control.
Data Source
AI summary
A semiconductor device is free from degradation of characteristics attributable to a manufacturing process thereof and its characteristics are hardly affected by changes in electric potentials of bonding pads. The semiconductor device 10 includes an active region 12, a first insulating layer 13 covering the active region 12, a floating conductor 14 formed on the first insulating layer 13, a second insulating layer 15 formed on the first insulating layer 13 and the floating conductor 14, a bonding pad 18 formed on the second insulating layer 17 and interconnection vias 19, 20 for electrically connecting the active region 12 and the bonding pad 18.