3D Semiconductor Bonding Pad Layout for Defect Probing
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Solution Overview
Problem
The integration degree of semiconductor devices has reached a limit with single-layer memory cells, necessitating the development of three-dimensional semiconductor devices with stacked memory cells to improve operation reliability.
Innovation Solution
A semiconductor device is designed with a substrate having a chip region and a pad region, featuring first and second bonding pads, and probing pads connected to the rear surfaces of the bonding pads. This configuration allows for the detection of bonding defects by applying different voltages to the probing pads.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If three-dimensional semiconductor devices with stacked memory cells are developed to improve integration degree, then the integration degree is improved, but the complexity of bonding processes and bonding defect detection increases
Solution Approach 1:
The patent applies preliminary action by forming probing pads that extend from the pad region into the chip region before the bonding process. These probing pads are pre-positioned to contact the rear surfaces of bonding pads on the stacked wafer, enabling subsequent defect detection without adding complexity to the bonding process itself. This advance preparation allows for quality control to be integrated seamlessly into the manufacturing flow.
Solution Approach 2:
The patent uses probing pads as intermediary elements between the external testing equipment and the bonding pads. These probing pads serve as mediators that transmit electrical signals to detect bonding defects. By introducing this intermediary structure, the patent enables non-destructive detection of bonding quality without requiring direct access to the bonded interfaces, thus managing the complexity of bonding process monitoring.
2Reliability
If probing pads are extended into the chip region to detect bonding defects, then the reliability is improved, but the manufacturing process complexity increases
Solution Approach 1:
The probing pads serve multiple functions: they act as electrical contacts for bonding pad connections and simultaneously serve as testing probes for defect detection. This multi-functionality reduces the need for separate testing structures, thereby limiting the increase in structural complexity while maintaining reliable bonding defect detection capability.
Solution Approach 2:
The patent merges the functions of electrical connection and defect detection into a single probing pad structure. By combining these two functions that would traditionally require separate components, the patent reduces overall structural complexity while achieving reliable bonding quality assessment.
3Productivity
If multiple wafers are stacked to improve integration degree, then the productivity is improved, but the difficulty of detecting bonding defects increases
Solution Approach 1:
The probing pads act as intermediary testing elements that provide direct electrical access to the bonding pads on stacked wafers. This intermediary structure enables simple voltage application and current measurement to detect bonding defects, transforming a complex inspection problem into a straightforward electrical test that can be performed efficiently on multi-wafer stacks.
Solution Approach 2:
The patent replaces complex mechanical or visual inspection methods for detecting bonding defects with simple electrical measurements. By applying voltages to probing pads and measuring resulting currents, the system substitutes elaborate detection mechanisms with efficient electrical testing, thereby maintaining productivity while improving defect detection capability.
Data Source
AI summary
A semiconductor device may include a substrate including a chip region and a pad region, first bonding pads positioned in the chip region, second bonding pads positioned on the first bonding pads and having a front surface connected to the first bonding pads, a first probing pad positioned in the pad region, extending to the chip region, and connected to a rear surface of at least one second bonding pad among the second bonding pads, and a second probing pad positioned neighbor the first probing pad and connected to the rear surface of at least one second bonding pad among the second bonding pads.