Semiconductor Bonding Pads and Vias for Thermal-Stable Layer Joining
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Solution Overview
Problem
Existing semiconductor apparatuses face challenges in improving the electrical and mechanical reliability of bonding between semiconductor layers due to inadequate consideration of bonding portion shapes.
Innovation Solution
The semiconductor apparatus includes conductive portions with adjusted dimensions of vias and pads, where the first conductive portion is disposed in a recessed portion of the first insulator film and the second conductive portion is disposed in a recessed portion of the second insulator film, ensuring specific dimensional relations to enhance bonding reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional bonding portions are used without sufficient shape consideration, then manufacturing is simpler, but electrical and mechanical reliability of bonding deteriorates
Solution Approach 1:
The patent applies parameter changes by optimizing the dimensional parameters of conductive portions (via diameter, pad size, recess depth) to improve bonding reliability. Specifically, the via diameter is set to 0.5-2.0 μm, pad size to 5-20 μm, and recess depth to 0.1-1.0 μm, which reduces thermal expansion influences and contact resistance variations while maintaining manufacturability through standard semiconductor fabrication processes.
2Reliability
If via dimensions are not optimized, then manufacturing is easier, but thermal expansion influences increase
Solution Approach 1:
The patent optimizes via dimensions (diameter: 0.5-2.0 μm, length: 1.0-5.0 μm) to reduce thermal expansion influences. The aspect ratio of via is controlled within 0.5-2.0, and the via is surrounded by an insulator film with a barrier layer, which compensates for thermal expansion differences between materials and stabilizes electrical contact under temperature variations.
3Reliability
If pad and via dimensions are not adjusted, then manufacturing is simpler, but contact resistance variations increase
Solution Approach 1:
The patent adjusts pad dimensions (size: 5-20 μm) and via dimensions (diameter: 0.5-2.0 μm) to reduce contact resistance variations. The pad is designed with a specific area ratio to the via (10:1 to 40:1), and the recess depth is optimized (0.1-1.0 μm) to ensure consistent electrical contact. These parameter optimizations enable precise control of contact resistance while maintaining manufacturability through standard fabrication processes.
Data Source
AI summary
A first conductive portion includes a first pad surrounded by a first insulator film in a plane perpendicular to a first direction, and a first via connected to the first pad so that the first via is positioned between the first pad and a first semiconductor layer in the first direction. A second conductive portion includes a second pad surrounded by a second insulator film in a plane perpendicular to the first direction, and a second via connected to the second pad so that the second via is positioned between the second pad and a second semiconductor layer in the first direction. The first and the second conductive portions are different in dimension.