Low-Temperature Bonding of Semiconductor Structures via Through-Wafer Interconnects
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Solution Overview
Problem
Current semiconductor bonding techniques, particularly for 3D integration, face challenges in achieving strong bonds at low temperatures to prevent damage to existing device structures, and in establishing efficient electrical connections between semiconductor structures with mismatched connections.
Innovation Solution
The method involves forming a semiconductor-on-insulator substrate with through wafer interconnects and multiple metallization layers to create continuous electrical pathways between semiconductor structures, allowing for direct bonding at low temperatures and facilitating the integration of semiconductor devices without damaging existing structures.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Strength
If direct metal-to-metal bonding is performed at high temperatures, then strong bonds are achieved between semiconductor structures, but existing device structures are damaged due to thermal stress
Solution Approach 1:
The patent applies parameter changes by transitioning from high-temperature bonding to low-temperature bonding processes. Specifically, it uses bonding temperatures below 400°C (and in some embodiments below 200°C) instead of conventional high-temperature processes, thereby achieving strong bonds without causing thermal damage to existing device structures.
Solution Approach 2:
The patent replaces thermal bonding mechanisms with mechanical bonding mechanisms. It employs direct metal-to-metal contact bonding at low temperatures, where mechanical pressure and surface contact replace the thermal diffusion processes that would otherwise be required to achieve strong bonds between semiconductor structures.
2Ease of operation
If carrier substrates are used to support thin semiconductor structures, then handling and processing are facilitated, but the overall device footprint and complexity increase
Solution Approach 1:
The patent merges the carrier substrate function with the bonding process itself. By integrating multiple semiconductor structures directly onto a common substrate through low-temperature bonding, the carrier substrate serves dual purposes: providing mechanical support during processing and serving as the final mounting platform for the bonded structures, thereby eliminating the need for separate carrier removal steps and reducing overall complexity.
3Reliability
If through wafer interconnects are formed to establish electrical connections between bonded structures, then electrical performance is improved, but manufacturing process complexity increases
Solution Approach 1:
The patent applies preliminary action by forming through wafer interconnects and metallization layers on the common substrate before bonding the semiconductor structures. This allows electrical connections to be pre-established and aligned, so that when structures are bonded together, the electrical pathways are already in place, simplifying the overall manufacturing process and improving connection reliability.
Data Source
AI summary
Methods of forming semiconductor devices include providing a substrate including a layer of semiconductor material on a layer of electrically insulating material. A first metallization layer is formed over a first side of the layer of semiconductor material. Through wafer interconnects are foamed at least partially through the substrate. A second metallization layer is formed over a second side of the layer of semiconductor material opposite the first side thereof. An electrical pathway is provided that extends through the first metallization layer, the substrate, and the second metallization layer between a first processed semiconductor structure carried by the substrate on the first side of the layer of semiconductor material and a second processed semiconductor structure carried by the substrate on the first side of the layer of semiconductor material. Semiconductor structures are fabricated using such methods.